IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 138

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–54
Table 5–30. Transceiver Control Signals (Part 2 of 2)
Table 5–31. Transceiver Control Signal Use c
PCI Express Compiler User Guide
reconfig_fromgxb[16:0]
reconfig_fromgxb[33:0]
reconfig_fromgxb
reconfig_togxb[3:0]
reconfig_togxb[2:0]
reconfig_clk
(Arria II GX, Arria II GZ,
Cyclone IV GX)
fixedclk
busy_reconfig_altgxb_
reconfig
reset_reconfig_altgxb_
reconfig
cal_blk_clk
reconfig_clk
reconfig_togxb
reconfig_fromgxb
Note to
(1) Stratix V GX uses a different mechanism to reconfigure transceiver settings.
(Stratix IV GX ×1 and ×4)
(Stratix IV GX ×8)
(Stratix II GX, Arria GX)
(Stratix IV GX)
(Stratix II GX, Arria GX)
Signal SOPC Builder
Signal SOPC Builder
Table
5–31:
f
The input signals listed in
transceiver instance.
For more information refer to the
User
Handbook, or
appropriate.
Non-
functional
Non-
functional
Non-
functional
Arria GX
Guide, the
Yes
I/O
O
O
I
I
I
I
I
I
AN 558: Implementing Dynamic Reconfiguration in Arria II GX Devices
Arria II GX
Transceiver Configuration Guide
These are the transceiver dynamic reconfiguration signals. Transceiver dynamic
reconfiguration is not typically required for PCI Express designs in Stratix II GX
or Arria GX devices. These signals may be used for cases in which the PCI
Express instance shares a transceiver quad with another protocol that supports
dynamic reconfiguration. They may also be used in cases where the transceiver
analog controls (V
modified to compensate for extended PCI Express interconnects such as cables.
In these cases, these signals must be connected as described in the
Device
tied low, reconfig_togxb tied to b'010 and reconfig_fromgxb left open.
For Arria II GX and Stratix IV GX devices, dynamic reconfiguration is required for
PCI Express designs to compensate for variations due to process, voltage and
temperature. You must connect the ALTGX_RECONFIG instance to the ALTGX
instances with receiver channels, in your design using these signals. The
maximum frequency of reconfig_clk is 50 MHz. For more information about
instantiating the ALTGX_RECONFIG megafunction in your design refer to
“Transceiver Offset Cancellation” on page
A 125 MHz free running clock that you must provide that serves as input to the
fixed clock of the transceiver. fixedclk and the 50 MHz reconfig_clk must be
free running and not derived from refclk. This signal is used in the hard IP
implementation for Arria II GX, Arria II GZ, Cyclone IV GX, HardCopy IV GX, and
Stratix IV GX devices.
When asserted, indicates that offset calibration is calibrating the transceiver. This
signal is used in the hard IP implementation for Arria II GX, Arria II GZ,
Cyclone IV GX, HardCopy IV GX, and Stratix IV GX devices.
This signal keeps the altgxb_reconfig block in reset till the reconfig_clk and
fixedclk are stable.
Yes
Yes
Yes
Yes
Handbook, otherwise, when unused, the reconfig_clk signal should
Cyclone IV GX
Table 5–31
Yes
Yes
Yes
Yes
OD
, Pre-emphasis, and Manual Equalization) need to be
Stratix II GX ALT2GXB_RECONFIG Megafunction
connect from the user application directly to the
HardCopy IV GX
Yes
Yes
Yes
Yes
Description
in volume 3 of the
Stratix II GX
13–9.
Yes
Yes
Yes
Yes
December 2010 Altera Corporation
Physical Layer Interface Signals
Stratix IV GX
Chapter 5: IP Core Interfaces
Stratix IV Device
Yes
Yes
Yes
Yes
Stratix II GX
Stratix V GX
No
No
No
No
(1)
as