IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 63

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: IP Core Architecture
Application Interfaces
December 2010 Altera Corporation
Table 4–1
implementations. As this table indicates, the Avalon-ST interface can be either 64 or
128 bits for the hard IP implementation. For the soft IP implementation, the Avalon-ST
interface is 64 bits.
Table 4–1. Application Clock Frequencies
×1
×4
×8
×1
×4
×8
×1
×4
×8
×1
×4
×8
×1
×2
×4
×1
×4
×8
Lanes
Lanes
Lanes
Lanes
Lanes
Lanes
Hard IP Implementation— Stratix IV GX, Hardcopy IV GX, and Stratix V GX/GS
provides the application clock frequencies for the hard IP and soft IP
125 MHz @ 64 bits
125 MHz @ 64 bits
250 MHz @ 64 bits or 125 MHz @ 128 bits
62.5 MHz @ 64 bits or 125 MHz @ 64 bits
125 MHz @ 64 bits
250 MHz @ 64 bits or 125 MHz @ 128 bits
62.5 MHz @ 64 bits or 125 MHz @ 64 bits
125 MHz @ 64 bits
125 MHz @ 128 bits
125 MHz @ 64 bits
125 MHz @ 64 bits
125 MHz @ 128 bits
62.5 MHz @ 64 bits or 125 MHz @ 64 bits
125 MHz @ 64 bits
125 MHz @ 64 bits
62.5 MHz @ 64 bits or 125 MHz @64 bits
125 MHz @ 64 bits
250 MHz @ 64 bits
Hard IP Implementation—Cyclone IV GX
Hard IP Implementation— Stratix V GX
Hard IP Implementation—Arria II GX
Hard IP Implementation—Arria II GZ
Soft IP Implementation
Gen1
Gen1
Gen1
Gen1
Gen1
Gen1
125 MHz @ 64 bits
250 MHz @ 64 bits or
125 MHz @ 128 bits
250 MHz @ 128 bits
125 MHz @ 64 bits
250 MHz @ 64 bits or
125 MHz @ 128 bits
250 MHz @ 128 bits
125 MHz @ 64 bits
125 MHz @ 128 bits
PCI Express Compiler User Guide
Gen2
Gen2
Gen2
Gen2
Gen2
Gen2
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