IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 22

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

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IP Core Verification
Performance and Resource Utilization
PCI Express Compiler User Guide
Simulation Environment
Compatibility Testing Environment
To ensure compliance with the PCI Express specification, Altera performs extensive
validation of the PCI Express IP cores. Validation includes both simulation and
hardware testing.
Altera’s verification simulation environment for the PCI Express IP cores uses
multiple testbenches that consist of industry-standard BFMs driving the PCI Express
link interface. A custom BFM connects to the application-side interface.
Altera performs the following tests in the simulation environment:
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Altera has performed significant hardware testing of the PCI Express IP cores to
ensure a reliable solution. The IP cores have been tested at various PCI-SIG PCI
Express Compliance Workshops in 2005–2009 with Arria GX, Arria II GX,
Cyclone IV GX, Stratix II GX, and Stratix IV GX devices and various external PHYs.
They have passed all PCI-SIG gold tests and interoperability tests with a wide
selection of motherboards and test equipment. In addition, Altera internally tests
every release with motherboards and switch chips from a variety of manufacturers.
All PCI-SIG compliance tests are also run with each IP core release.
The hard IP implementation of the PCI Express IP core is available in Arria II GX,
Cyclone IV GX, HardCopy IV GX, Stratix IV GX, and Stratix V devices.
Directed tests that test all types and sizes of transaction layer packets and all bits of
the configuration space
Error injection tests that inject errors in the link, transaction layer packets, and data
link layer packets, and check for the proper response from the IP cores
PCI-SIG Compliance Checklist tests that specifically test the items in the checklist
Random tests that test a wide range of traffic patterns across one or more virtual
channels
December 2010 Altera Corporation
Chapter 1: Datasheet
IP Core Verification