IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 31

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
Parameterize the PCI Express
Figure 2–3. Credit Allocation Table (Read-Only)
December 2010 Altera Corporation
1
12. Click the Buffer Setup tab to open the Buffer Setup page.
Table 2–4. Buffer Setup Parameters
For the PCI Express hard IP implementation, the RX Buffer Space Allocation is fixed
at Maximum performance. This setting determines the values for a read-only table
that lists the number of posted header credits, posted data credits, non-posted header
credits, completion header credits, completion data credits, total header credits, and
total RX buffer space.
13. Click Next to display the Power Management page.
Table 2–5. Power Management Parameters (Part 1 of 2)
Maximum payload size
Number of virtual channels
Number of low-priority VCs
Auto configure retry buffer size
Retry buffer size
Maximum retry packets
Desired performance for received requests
Desired performance for received completions
Idle threshold for L0s entry
correct settings for this page.
correct settings for this page.
Parameter
Parameter
Figure 2–3
L0s Active State Power Management (ASPM)
shows the Credit Allocation Table.
8,192 ns
512 bytes
1
None
On
16 KBytes
64
Maximum
Maximum
Fixed according to the
device chosen for
hard IP implementation
Table 2–5
PCI Express Compiler User Guide
Table 2–4
Value
Value
describes the
provides the
2–5