IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 62

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–4
Figure 4–3. PCI Express Hard IP Implementation with Avalon-ST Interface to User Application
Figure 4–4. PCI Express Soft IP Implementation with Avalon-ST Interface to User Application
PCI Express Compiler User Guide
Transceiver
Transceiver
PIPE
PIPE
■
PCI Express Hard IP Core
PHYMAC
The hard IP implementation includes the following interfaces to access the
configuration space registers:
■
■
■
PCI Express Soft IP Core
PHYMAC
The LMI interface
The Avalon-MM PCIe reconfig bus which can access any read-only
configuration space register
In root port configuration, you can also access the configuration space registers
with a configuration type TLP using the Avalon-ST interface. A type 0
configuration TLP is used to access the RP configuration space registers, and a
type 1 configuration TLP is used to access the configuration space registers of
downstream nodes, typically endpoints on the other side of the link.
Crossing
Domain
(CDC)
Clock
Data
Layer
(DLL)
Link
Data
Layer
(DLL)
Link
Transaction Layer
Clock & Reset
Selection
(TL)
Transaction Layer
Clock & Reset
Configuration
Selection
(TL)
Space
Reconfig
Test
Block
Adapter
Test_in/Test_out
LMI
Adapter
Avalon-ST Rx
Avalon-ST Tx
December 2010 Altera Corporation
PCIe Reconfig
(Avalon-MM)
Side Band
Chapter 4: IP Core Architecture
Avalon-ST Rx
Avalon-ST Tx
Side Band
LMI
Application Interfaces