IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 206

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

12–6
Table 12–5. Parity Error Conditions
PCI Express Compiler User Guide
Detected parity error (status register bit 15)
Master data parity error (status register bit 8)
Status Bit
Poisoned transaction layer packets can also set the parity error bits in the PCI
configuration space status register.
errors.
Poisoned packets received by the IP core are passed to the application layer. Poisoned
transmit transaction layer packets are similarly sent to the link.
Set when any received transaction layer packet is poisoned.
This bit is set when the command register parity enable bit is set and one of
the following conditions is true:
■
■
The poisoned bit is set during the transmission of a write request
transaction layer packet.
The poisoned bit is set on a received completion transaction layer packet.
Table 12–5
lists the conditions that cause parity
Conditions
December 2010 Altera Corporation
Error Reporting and Data Poisoning
Chapter 12: Error Handling