IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 11

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Table 1–1. PCI Express Throughput
Features
December 2010 Altera Corporation
December 2010
<edit Part Number variable in chapter>
PCI Express Gen1 Gbps (1.x compliant)
PCI Express Gen2 Gbps (2.0 compliant)
f
This document describes Altera’s IP core for PCI Express. PCI Express is a
high-performance interconnect protocol for use in a variety of applications including
network adapters, storage area networks, embedded controllers, graphic accelerator
boards, and audio-video products. The PCI Express protocol is software
backwards-compatible with the earlier PCI and PCI-X protocols, but is significantly
different from its predecessors. It is a packet-based, serial, point-to-point interconnect
between two devices. The performance is scalable based on the number of lanes and
the generation that is implemented. Altera offers both endpoints and root ports that
are compliant with
Base Specification 2.0
configurable hard IP block rather than programmable logic, saving significant FPGA
resources. The PCI Express IP core is available in ×1, ×2, ×4, and ×8 configurations.
Table 1–1
PCI Express IP cores for 1, 2, 4, and 8 lanes. The protocol specifies 2.5 giga-transfers
per second for Gen1 and 5 giga-transfers per second for Gen2. Because the PCI
Express protocol uses 8B10B encoding, there is a 20% overhead which is included in
the figures in
so that the numbers in
Refer to the
the hard IP implementation in Stratix
Altera’s PCI Express IP core offers extensive support across multiple device families.
If supports the following key features:
■
■
Hard IP
protocol stack including the transaction, data link, and physical layers is hardened
in the device.
Soft IP implementation:
■
■
■
PCI Express Base Specification 1.0a or 1.1.
Many other device families supported. Refer to
The PCI Express protocol stack including transaction, data link, and physical
layer is implemented using FPGA fabric logic elements
shows the aggregate bandwidth of a PCI Express link for Gen1 and Gen2
implementation—PCI Express Base Specification 1.1 or
PCI Express High Performance Reference Design
Table
PCI Express Base Specification 1.0a or 1.1
1–1.
for Gen2. Both endpoints and root ports can be implemented as a
Table 1–1
Table 1–1
×1
2
4
would be doubled for duplex operation.
provides bandwidths for a single TX or RX channel,
®
IV GX and Arria
×2
8
4
Link Width
Table
®
II GX devices.
for bandwidth numbers for
for Gen1 and
×4
16
8
1–4.
PCI Express Compiler User Guide
1. Datasheet
2.0. The PCI Express
PCI Express
×8
16
32