IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 66

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–8
PCI Express Compiler User Guide
1
1
For example, you may want to send an MSI request only after all TX packets are
issued to the transaction layer. Alternatively, if you cannot interrupt traffic flow to
synchronize the MSI, you can use a counter to count 16 writes (the depth of the FIFO)
after a TX packet has been written to the FIFO (or until the FIFO goes empty) to
ensure that the transaction layer interface receives the packet before issuing the MSI
request.
Because the Stratix V devices do not include the adapter module, MSI
synchronization is not necessary for Stratix V devices.
Figure 4–5. Avalon-ST TX and MSI Datapaths, Arria II GX, Cyclone IV GX, HardCopy IV GX, and
Stratix IV GX Devices
Incremental Compilation
The IP core with Avalon-ST interface includes a fully registered interface between the
user application and the PCI Express transaction layer. For the soft IP implementation,
you can use incremental compilation to lock down the placement and routing of the
PCI Express IP core with the Avalon-ST interface to preserve placement and timing
while changes are made to your application.
Incremental recompilation is not necessary for the PCI Express hard IP
implementation. This implementation is fixed. All signals in the hard IP
implementation are fully registered.
Figure 4–5
To Application
Layer
(from Transaction Layter)
Non-Posted Requests
tx_cred0 for Completion
and Posted Requests
tx_cred0 for
illustrates the Avalon-ST TX and MSI datapaths.
tx_fifo_empty0
tx_fifo_wrptr0
tx_fifo_rdptr0
app_msi_req
tx_st_data0
Non-Posted Credits
FIFO
December 2010 Altera Corporation
Chapter 4: IP Core Architecture
To Transaction
Layer
Application Interfaces