IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 140

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–56
Figure 5–43. Two PCI Express ×8 Links in a Four Transceiver Block Device
Note to
(1) This connectivity is specified in <variation>_serdes.<v or vhd>
PCI Express Compiler User Guide
PCI Express Lane 7
PCI Express Lane 6
PCI Express Lane 5
PCI Express Lane 4
PCI Express Lane 3
PCI Express Lane 2
PCI Express Lane 1
PCI Express Lane 0
Figure
PIPE Interface Signals
5–43:
f
f
1
assigned in order to the pins associated with channels 0-3 of the Slave Transceiver
Block. The signals rx_in[4]/tx_out[4] must be assigned to the pins associated with
channel 0 of the Slave Transceiver Block, rx_in[5]/tx_out[5] must be assigned to
the pins associated with channel 1 of the Slave Transceiver Block, and so on.
Figure 5–43
You must verify the location of the master transceiver block before making pin
assignments for the hard IP implementation of the PCI Express IP core.
Refer to
.pdf, .txt, and .xls formats.
Refer to Volume 2 of the
Handbook,
Handbook, or the “Transceiver Clocking and Channel Placement Guidelines” in for
more information about the transceiver blocks.
The ×1 and ×4 soft IP implementation of the IP core is compliant with the 16-bit
version of the PIPE interface, enabling use of an external PHY. The ×8 soft IP
implementation of the IP core is compliant with the 8-bit version of the PIPE interface.
These signals are available even when you select a device with an internal PHY so that
you can simulate using both the one-bit and the PIPE interface. Typically, simulation
is much faster using the PIPE interface. For hard IP implementations, the 8-bit PIPE
interface is also available for simulation purposes. However, it is not possible to use
the hard IP PIPE interface in an actual device.
signals used for a standard 16-bit SDR or 8-bit SDR interface. These interfaces are used
Transceiver Block GXBL0
Stratix IV GX Device
Transceiver Block GXBL1
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
(Master)
(Slave)
Pin-out Files for Altera Devices
the
illustrates this connectivity.
Stratix II GX Transceiver User
Second PCI
Arria GX Device
Express
(PIPE)
x8 Link
First PCI
Express
(PIPE)
x8 Link
for pin-out tables for all Altera devices in
Handbook, Volume 2 of
Guide, or Volume 2 of the
Table 5–33
Transceiver Block GXBR1
Transceiver Block GXBR0
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
(Master)
(Slave)
describes the PIPE interface
December 2010 Altera Corporation
Physical Layer Interface Signals
Chapter 5: IP Core Interfaces
Arria II Device
Stratix IV Device
PCI Express Lane 7
PCI Express Lane 6
PCI Express Lane 5
PCI Express Lane 4
PCI Express Lane 3
PCI Express Lane 2
PCI Express Lane 1
PCI Express Lane 0