IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 355

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Additional Information
Revision History
December 2010 Altera Corporation
February 2010
November
2009
November
2009
(continued)
March 2009
Date
9.1 SP1
Version
9.1
9.1
9.0
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Added support of Cyclone IV GX ×2.
Added r2c_err0 and r2c_err1 signals to report uncorrectable ECC errors for the hard IP
implementation with Avalon-ST interface.
Added suc_spd_neg signal for all hard IP implementations which indicates successful
negotiation to the Gen2 speed.
Added support for 125 MHz input reference clock (in addition to the 100 MHz input
reference clock) for Gen1 for Arria II GX, Cyclone IV GX, HardCopy IV GX, and Stratix IV GX
devices.
Added new entry to
MM interface for Stratix IV GX Gen2 ×1 is available in the -2 and -3 speed grades.
Corrected entries in
also generated by the core with application layer. For PCI Base Specification 1.1 or 2.0 hot
plug messages are not transmitted to the application layer.
Clarified mapping of message TLPs. They use the standard 4 dword format for all TLPs.
Corrected field assignments for device_id and revision_id in
Removed documentation for BFM Performance Counting in the Testbench chapter; these
procedures are not included in the release.
Updated definition of rx_st_bardec<n> to say that this signal is also ignored for message
TLPs. Updated
of this signal.
Added support for Cyclone IV GX and HardCopy IV GX.
Added ability to parameterize the ALTGX Megafunction from the PCI Express IP core.
Added ability to run the hard IP implementation Gen1 ×1 application clock at 62.5 MHz,
presumably to save power.
Added the following signals to the IP core: xphy_pll_areset, xphy_pll_locked,
nph_alloc_1cred_vc0, npd_alloc_1cred_vc1, npd_cred_vio_vc0, and
nph_cred_vio_vc1
Clarified use of qword alignment for TLPs in
Updated
Express configuration register table and provide more information about the various fields.
Corrected definition of the definitions of cfg_devcsr[31:0] in
cfg_devcsr[31:16] is device status. cfg_devcsr[15:0] is device control.
Corrected definition of Completer abort in
cpl_error[2].
Added 2 unexpected completions to
Updated
Added detailed description of the tx_cred<n> signal.
Corrected
Expanded discussion of
Clarified
internal clock of the ×8 core runs at 500 MHz.
Added warning about use of test_out and test_in buses.
Moved debug signals rx_st_fifo_full0 and rx_st_fifo_empty0 to the test bus.
Documentation for these signals moved from the Signals chapter to
Interface
Table 1–9 on page
Table 5–16 on page 5–37
Figure 7–12 on page 7–15
Signals.
Table 3–2 on page
Figure 5–9 on page 5–11
Table 1–9 on page
Table 9–2 on page
“Serial Interface Signals” on page
1–14. All cores support ECC with the exception of Gen2 ×8. The
3–5. Expansion ROM is non-prefetchable.
to include cross-references to the appropriate PCI
to show clk and AvlClk_L.
Table 12–4 on page
Changes Made
1–14. The hard IP implementation using the Avalon-
9–2, as follows: Assert_INTA and Deassert_INTA are
and
Table 12–4 on page
Chapter 5, IP Core
Figure 5–10 on page 5–11
12–3.
5–55.
Table 13–1 on page
12–3. The error is reported on
Interfaces.
Table 5–16 on page
PCI Express Compiler User Guide
Appendix B, Test Port
to show the timing
13–2.
5–37.
Info–3
SPR