IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 143

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: IP Core Interfaces
Test Signals
Table 5–35. Test Interface Signals—Hard IP Implementation
December 2010 Altera Corporation
test_in[39:0] (hard IP)
test_out[63:0] or [8:0]
Note to
(1) All signals are per lane.
(2) Refer to
Table
Test Interface Signals—Hard IP Implementation
“PIPE Interface Signals” on page 5–57
5–35:
Signal
for definitions of the PIPE interface signals.
I/O
O
I
The test_in bus provides runtime control for specific IP core
features. For normal operation, this bus can be driven to all 0's. The
following bits are defined:
[0]—Simulation mode. This signal can be set to 1 to accelerate
initialization by changing many initialization count.
[4:1]—reserved.
[6:5] Compliance test mode. Disable/force compliance mode:
■
■
[11:8]— b’0011.
[15:13]—lane select.
[31:16, 12]—reserved.
[32] Compliance mode test switch. When set to 1, the IP core is in
compliance mode which is used for Compliance Base Board testing
(CBB) testing. When set to 0, the IP core is in operates normally.
Connect this signal to a switch to turn on and off compliance mode.
Refer to the
actual coding example to specify CBB tests.
The test_out bus allows you to monitor the PIPE interface.
If you select the 9-bit test_out bus width, a subset of the 64-bit test
bus is brought out as follows:
■
■
The following bits are defined:
■
■
■
■
■
■
■
■
■
■
■
bit 0—when set, prevents the LTSSM from entering compliance
mode. Toggling this bit controls the entry and exit from the
compliance state, enabling the transmission of Gen1 and Gen2
compliance patterns.
bit 1—forces compliance mode. Forces entry to compliance mode
when timeout is reached in polling.active state (and not all lanes
have detected their exit condition).
bits [8:5] = test_out[28:25]Reserved.
bits [4:0] = test_out[4:0] txdata[3:0]
[7:0]—txdata
[8]—txdatak
[9]—txdetectrx
[10]—txelecidle
[11]—txcompl
[12]—rxpolarity
[14:13]—powerdown
[22:15]—rxdata
[23]—rxdatak
[24]—rxvalid
[63:25]—Reserved.
PCI Express High Performance Reference Design
Description
PCI Express Compiler User Guide
(1) (2)
for an
5–59