IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 149

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Register Descriptions
Configuration Space Register Content
Table 6–8. PCI Express Capability Structure Version 2.0, Rev2 Spec: PCI Express Capabilities Register and PCI Express
Capability List Register
Table 6–9. Virtual Channel Capability Structure, Rev2 Spec: Virtual Channel Capability (Part 1 of 2)
December 2010 Altera Corporation
0x080
0x084
0x088
0x08C
0x090
0x094
0x098
0x09C
0x0A0
0x0A4
0x0A8
0x0AC
0x0B0
0x0B4
0x0B8
Note to
(1) Registers not applicable to a device are reserved.
(2) Refer to
0x100
0x104
0x108
0x10C
0x110
0x114
0x118
0x11C
0x120
0x124
0x164
Byte Offset
Base Specification 2.0.
Byte Offset
Table
Table 6–23 on page 6–12
6–8:
Table 6–8
Table 6–9
Next Cap PTR
ReservedP
VAT offset
Port VC Status
PAT offset 0 (31:24)
VC Resource Control Register (0)
VC Resource Status Register (0)
PAT offset 1 (31:24)
VC Resource Control Register (1)
VC Resource Status Register (1)
...
PAT offset 7 (31:24)
PCI Express Capabilities Register
for a comprehensive list of correspondences between the configuration space registers and the
31:24
describes the PCI Express capability structure for specification version 2.0.
describes the virtual channel capability structure.
Root Capabilities
Device Status 2
Device Status
Link Status 2
Slot Status 2
Link Status
Slot Status
31:16
ReservedP
VC Resource Capability Register (0)
VC Resource Capability Register (1)
VC Resource Capability Register (7)
23:16
Device Capabilities 2
Device Capabilities
Link Capabilities 2
Slot Capabilities 2
Vers.
Link Capabilities
Slot Capabilities
Root Status
Extended Cap ID
Port VC Cap 1
Number of low-priority VCs
ReservedP
ReservedP
Port VC control
Next Cap Pointer
Implement completion timeout disable
15:8
15:8
Device Control 2
Device Control 2
Link Control 2
Slot Control 2
Root Control
Link Control
Slot Control
PCI Express Compiler User Guide
VC arbit. cap
PCI Express Cap ID
7:0
7:0
PCI Express
6–5