IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 243

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 15: Testbench and Design Example
Chaining DMA Design Example
Table 15–6. Bit Definitions for the Control Field in the DMA Write Control Register and DMA Read Control Register
Table 15–7. Chaining DMA Status Register Definitions
Table 15–8. Fields in the DMA Write Status High Register
December 2010 Altera Corporation
[30:28]
31
Addr
Note to
(1) This is the endpoint byte address offset from BAR2 or BAR3.
[31:28]
[27:26]
[25:24]
0x2C
0x20
0x24
0x28
0x30
Bit
Bit
(2)
Table
MSI Traffic Class
DT RC Last Sync
CDMA version
Core type
Reserved
Register Name
DMA Wr Status Hi
DMA Wr Status Lo
DMA Rd Status Hi
DMA Rd Status Lo
Error Status
15–7:
Field
Table 15–7
Table 15–8
read only.
Field
defines the DMA status registers. These registers are read only.
describes the fields of the DMA write status register. All of these fields are
When the RC application software reads the MSI capabilities of the endpoint, this
value is assigned by default to MSI traffic class 0. These register bits map to the
PCI Express back-end signal app_msi_tc[2:0].
When 0, the DMA engine stops transfers when the last descriptor has been
executed. When 1, the DMA engine loops infinitely restarting with the first
descriptor when the last descriptor is completed. To stop the infinite loop, set this
bit to 0.
3124
Target Mem Address
Max No. of Tags
Identifies the version of the chaining DMA example design.
Identifies the core interface. The following encodings are defined:
■
■
■
Width
01 Descriptor/Data Interface
10 Avalon-ST soft IP implementation
00 Other
Reserved
For field definitions refer to
For field definitions refer to
2316
Write DMA Performance Counter. (Clock cycles from
time DMA header programmed until last descriptor
completes, including time to fetch descriptors.)
Read DMA Performance Counter. The number of clocks
from the time the DMA header is programmed until the
last descriptor completes, including the time to fetch
descriptors.
Description
Description
—
Table 15–8
Table 15–9
150
Error Counter. Number of bad
ECRCs detected by the
application layer. Valid only
when ECRC forwarding is
enabled.
PCI Express Compiler User Guide
15–15