IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 157

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Register Descriptions
Comprehensive Correspondence between Config Space Registers and PCIe Spec Rev 2.0
Table 6–23. Correspondence Configuration Space Registers and PCI Express Base Specification Rev. 2.0 Description
December 2010 Altera Corporation
Byte Address
0x0B8:0x0FC
0x094:0x0FF
0x100:0x16C
0x170:0x17C
0x180:0x1FC
0x200:0x23C
0x240:0x27C
0x280:0x2BC
0x2C0:0x2FC
0x300:0x33C
0x340:0x37C
0x380:0x3BC
0x3C0:0x3FC
0x400:0x7FC
0x800:0x834
0x838:0xFFF
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x000
0x004
0x008
0x00C
0x010
Table 6-3.
Table 6-2.
PCI Type 1 Configuration Space Header (Root Ports) , Rev2 Spec: Type 1 Configuration Space Header
PCI Type 0 Configuration Space Header (Endpoints), Rev2 Spec: Type 0 Configuration Space Header
Config Reg Offset 31:24 23:16 15:8 7:0
Reserved
Root port
Virtual channel capability structure
Reserved
Virtual channel arbitration table
Port VC0 arbitration table (Reserved)
Port VC1 arbitration table (Reserved)
Port VC2 arbitration table (Reserved)
Port VC3 arbitration table (Reserved)
Port VC4 arbitration table (Reserved)
Port VC5 arbitration table (Reserved)
Port VC6 arbitration table (Reserved)
Port VC7 arbitration table (Reserved)
Reserved
Advanced Error Reporting AER (optional)
Reserved
Device ID Vendor ID
Status Command
Class Code Revision ID
0x00 Header Type 0x00 Cache Line Size
Base Address 0
Base Address 1
Base Address 2
Base Address 3
Base Address 4
Base Address 5
Reserved
Subsystem Device ID Subsystem Vendor ID
Expansion ROM base address
Reserved Capabilities PTR
Reserved
0x00 0x00 Interrupt Pin Interrupt Line
Device ID Vendor ID
Status Command
Class Code Revision ID
BIST Header Type Primary Latency Timer Cache
Line Size
Base Address 0
Corresponding Section in PCIe Specification
Virtual Channel Capability
VC Arbitration Table
Port Arbitration Table
Port Arbitration Table
Port Arbitration Table
Port Arbitration Table
Port Arbitration Table
Port Arbitration Table
Port Arbitration Table
Port Arbitration Table
PCIe spec corresponding section name
Advanced Error Reporting Capability
Type 0 Configuration Space Header
Type 0 Configuration Space Header
Type 0 Configuration Space Header
Type 0 Configuration Space Header
Base Address Registers (Offset 10h - 24h)
Base Address Registers (Offset 10h - 24h)
Base Address Registers (Offset 10h - 24h)
Base Address Registers (Offset 10h - 24h)
Base Address Registers (Offset 10h - 24h)
Base Address Registers (Offset 10h - 24h)
Type 0 Configuration Space Header
Type 0 Configuration Space Header
Type 0 Configuration Space Header
Type 0 Configuration Space Header
Type 0 Configuration Space Header
Type 0 Configuration Space Header
Type 1 Configuration Space Header
Type 1 Configuration Space Header
Type 1 Configuration Space Header
Type 1 Configuration Space Header
Base Address Registers (Offset 10h/14h)
PCI Express Compiler User Guide
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