IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 264

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

15–36
Table 15–25. ebfm_barrd_wait Procedure
Table 15–26. ebfm_barrd_nowt Procedure
PCI Express Compiler User Guide
Location
Syntax
Arguments
Location
Syntax
Arguments
ebfm_barrd_wait(bar_table, bar_num, pcie_offset, lcladdr, byte_len, tclass)
bar_table
bar_num
pcie_offset
lcladdr
byte_len
tclass
altpcietb_bfm_rdwr.v or altpcietb_bfm_rdwr.vhd
ebfm_barrd_nowt(bar_table, bar_num, pcie_offset, lcladdr, byte_len, tclass)
bar_table
bar_num
pcie_offset
lcladdr
byte_len
tclass
altpcietb_bfm_rdwr.v or altpcietb_bfm_rdwr.vhd
ebfm_barrd_wait Procedure
The ebfm_barrd_wait procedure reads a block of data from the offset of the specified
endpoint BAR and stores it in BFM shared memory. The length can be longer than the
configured maximum read request size; the procedure breaks the request up into
multiple transactions as needed. This procedure waits until all of the completion data
is returned and places it in shared memory.
ebfm_barrd_nowt Procedure
The ebfm_barrd_nowt procedure reads a block of data from the offset of the specified
endpoint BAR and stores the data in BFM shared memory. The length can be longer
than the configured maximum read request size; the procedure breaks the request up
into multiple transactions as needed. This routine returns as soon as the last read
transaction has been accepted by the VC interface module, allowing subsequent reads
to be issued immediately.
Address of the endpoint bar_table structure in BFM shared memory. The
bar_table structure stores the address assigned to each BAR so that the driver code
does not need to be aware of the actual assigned addresses only the application
specific offsets from the BAR.
Number of the BAR used with pcie_offset to determine PCI Express address.
Address offset from the BAR base.
BFM shared memory address where the read data is stored.
Length, in bytes, of the data to be read. Can be 1 to the minimum of the bytes
remaining in the BAR space or BFM shared memory.
Traffic class used for the PCI Express transaction.
Address of the endpoint bar_table structure in BFM shared memory.
Number of the BAR used with pcie_offset to determine PCI Express address.
Address offset from the BAR base.
BFM shared memory address where the read data is stored.
Length, in bytes, of the data to be read. Can be 1 to the minimum of the bytes
remaining in the BAR space or BFM shared memory.
Traffic Class to be used for the PCI Express transaction.
Chapter 15: Testbench and Design Example
December 2010 Altera Corporation
BFM Procedures and Functions