IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 106

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–22
Figure 5–25. Avalon-ST TX Interface Timing
Notes to
(1) The maximum allowed response time is 3 clock cycles for the soft IP implementation and 2 clock cycles for the hard IP implementation.
PCI Express Compiler User Guide
Figure
Root Port Mode Configuration Requests
ECRC Forwarding
5–25:
tx_st_data0[63:0]
Figure 5–25
tx_st_ready <n> to throttle the application which is the source.
To ensure proper operation when sending CFG0 transactions in root port mode, the
application should wait for the CFG0 to be transferred to the IP core’s configuration
space before issuing another packet on the Avalon-ST TX port. You can do this by
waiting at least 10 clocks from the time the CFG0 SOP is issued on Avalon-ST and
then checking for tx_fifo_empty0==1 before sending the next packet.
If your application implements ECRC forwarding, it should not apply ECRC
forwarding to CFG0 packets that it issues on Avalon-ST. There should be no ECRC
appended to the TLP, and the TD bit in the TLP header should be set to 0. These
packets are internally consumed by the IP core and are not transmitted on the PCI
Express link.
On the Avalon-ST interface, the ECRC field follows the same alignment rules as
payload data. For packets with payload, the ECRC is appended to the data as an extra
dword of payload. For packets without payload, the ECRC field follows the address
alignment as if it were a one dword payload. Depending on the address alignment,
Figure 5–8 on page 5–10
the ECRC data for RX data.
page 5–20
payload data, the ECRC would correspond to Data0 in these figures.
tx_st_ready
tx_st_valid
tx_st_eop
tx_st_sop
clk
1
illustrate the position of ECRC data for TX data. For packets with no
illustrates the timing of the Avalon-ST TX interface. The core can deassert
2
3
4
through
5
cycle 1 cycle 2 cycle 3
Figure 5–16 on page 5–18
6
Figure 5–13 on page 5–12
7
8
response_time
cycle 4
9
10
11
through
. . .
12
cycle n
illustrate the position of
December 2010 Altera Corporation
13
Figure 5–22 on
Chapter 5: IP Core Interfaces
Avalon-ST Interface