IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 220

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

14–4
Figure 14–3. 8-Bit DDR Mode without Transmit Clock
PCI Express Compiler User Guide
8-bit DDR with a Source Synchronous TXClk
clk125_in
clk125_out
External connection
in user logic
refclk (pclk)
txdata
■
An edge detect circuit detects the relationships between the 125 MHz clock and the
250 MHz rising edge to properly sequence the 16-bit data into the 8-bit output
register.
Figure 14–4
synchronous transmit clock (TXClk). It is included in the file <variation name>.v or
<variation name>.vhd and includes a PLL. refclk (pclk from the external PHY) drives
the PLL inclock. The PLL inclock has the following outputs:
■
■
■
rxdata
source file referenced in your variation file from the <path>/ip/PCI Express
Compiler/lib directory, where <path> is the directory in which you installed the
PCI Express Compiler, to your project directory. Then use the MegaWizard Plug In
Manager to edit the PLL source file to set the required phase shift. Then add the
modified PLL source file to your Quartus II project.
An optional 62.5 MHz TLP Slow clock is provided for ×1 implementations.
A zero delay copy of the 125 MHz refclk used as the clk125_in for the IP core
and also to clock DDR input registers for the RX data and status signals.
A 250 MHz early clock. This PLL output clocks an 8-bit SDR transmit data output
register. It is multiplied from the 125 MHz refclk and is early in relation to the
refclk. A 250 MHz single data rate register for the 125 MHz DDR output allows
you to use the SDR output registers in the Cyclone II I/O block.
An optional 62.5 MHz TLP Slow clock is provided for ×1 implementations.
shows the implementation of the 8-bit DDR mode with a source
A
D
Q
Q
Mode 3
& Sync
Detect
DDIO
Edge
1
4
ENB
PLL
ENB
Q
Q
A
D
1
4
Q
Q
1
4
ENB
clk250_early
A
D
out txclk
tlp_clk
txdata_h
txdata_l
clk125_in
tlp_clk
refclk
MegaCore Function
December 2010 Altera Corporation
PCI Express
clk125_out
Chapter 14: External PHYs
External PHY Support