IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 252

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

15–24
PCI Express Compiler User Guide
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<variation_name>_example_rp_pipen1b.v—the top-level of the root port design
example that you use for simulation. This module instantiates the root port PCI
Express IP core variation, <variation_name>.v, and the root port application
altpcietb_bfm_vc_intf_ast. This module provides both PIPE and serial interfaces
for the simulation environment. This module has two debug ports named
test_out_icm (which is the test_out signal from the IP core) and test_in which
allows you to monitor and control internal states of the PCI Express IP core
variation. (Refer to
<variation_name>_example_rp_top.v—the top level of the root port example
design that you use for synthesis. The file instantiates
<variation_name>_example_rp_pipen1b.v. Note, however, that the synthesized
design only contains the PCI Express variant, and not the application layer,
altpcietb_bfm_vc_intf_ast. Instead, the application is replaced with dummy
signals in order to preserve the variant's application interface. This module is
provided so that you can compile the variation in the Quartus II software.
altpcietb_bfm_vc_intf_ast.v—a wrapper module which instantiates either
altpcietb_vc_intf_ast_64 or altpcietb_vc_intf_ast_128 based on the type of
Avalon-ST interface that is generated. It also instantiates the ECRC modules
altpcierd_cdma_ecrc_check and altpcierd_cdma_ecrc_gen which are used when
ECRC forwarding is enabled.
altpcietb_vc_intf_ast_64.v and altpcietb_vc_intf_ast_128.v—provide the interface
between the PCI Express variant and the root port BFM tasks. They provide the
same function as the altpcietb_vc_intf.v module, transmitting PCI Express
requests and handling completions. Refer to the
for a full description of this function. This version uses Avalon-ST signalling with
either a 64- or 128-bit data bus to the PCI Express IP core variation. There is one
VC interface per virtual channel.
altpcietb_bfm_vc_intf_ast_common.v—contains tasks called by
altpcietb_vc_intf_ast_64.v and altpcietb_vc_intf_ast_128.v
altpcierd_cdma_ecrc_check.v—checks and removes the ECRC from TLPs
received on the Avalon-ST interface of the PCI Express IP core variation. Contains
the following submodules:
altpcierd_cdma_ecrc_check_64.v, altpcierd_rx_ecrc_64.v, altpcierd_rx_ecrc_64.vo,
altpcierd_rx_ecrc_64_altcrc.v, altpcierd_rx_ecrc_128.v, altpcierd_rx_ecrc_128.vo,
altpcierd_rx_ecrc_128_altcrc.v. Refer to the
page 15–6
altpcierd_cdma_ecrc_gen.v—generates and appends ECRC to the TLPs
transmitted on the Avalon-ST interface of the PCI Express variant. Contains the
following submodules:
altpcierd_cdma_ecrc_gen_calc.v, altpcierd_cdma_ecrc_gen_ctl_64.v,
altpcierd_cdma_ecrc_gen_ctl_128.v, altpcierd_cdma_ecrc_gen_datapath.v,
altpcierd_tx_ecrc_64.v, altpcierd_tx_ecrc_64.vo, altpcierd_tx_ecrc_64_altcrc.v,
altpcierd_tx_ecrc_128.v, altpcierd_tx_ecrc_128.vo, altpcierd_tx_ecrc_128_altcrc.v,
altpcierd_tx_ecrc_ctl_fifo.v, altpcierd_tx_ecrc_data_fifo.v,
altpcierd_tx_ecrc_fifo.v Refer to the
page 15–6
for a description of these submodules
for a description of these submodules.
“Test Signals” on page
“Chaining DMA Design Example” on
5–58.)
“Chaining DMA Design Example” on
“Root Port BFM” on page 15–26
Chapter 15: Testbench and Design Example
December 2010 Altera Corporation
Root Port Design Example