IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 218

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

14–2
Figure 14–1. 16-bit SDR Mode - 125 MHz without Transmit Clock
PCI Express Compiler User Guide
16-bit SDR Mode with a Source Synchronous TXClk
clk125_out
clk125_in
1
External connection
in user logic
The refclk is the same as pclk, the parallel clock provided by the external PHY. This
document uses the terms refclk and pclk interchangeably.
■
■
■
The implementation of the 16-bit SDR mode with a source synchronous TXClk is
shown in
name>.vhd. In this mode the following clocking scheme is used:
■
■
clk125_out is a 125 MHz output that has the same phase-offset as refclk. The
clk125_out must drive the clk125_in input in the user logic as shown in the
Figure
is used to drive the clk125_in input of the IP core.
clk125_early is a 125 MHz output that is phase shifted. This phase-shifted output
clocks the output registers of the transmit data. Based on your board delays, you
may need to adjust the phase-shift of this output. To alter the phase shift, copy the
PLL source file referenced in your variation file from the <path>/ip/PCI Express
Compiler/lib directory, where <path> is the directory in which you installed the
PCI Express Compiler, to your project directory. Then use the MegaWizard Plug In
Manager in the Quartus II software to edit the PLL source file to set the required
phase shift. Then add the modified PLL source file to your Quartus II project.
tlp_clk62p5 is a 62.5 MHz output that drives the tlp_clk input of the IP core
when the MegaCore internal clock frequency is 62.5 MHz.
refclk is used as the clk125_in for the core
refclk clocks a single data rate register for the incoming receive data
refclk (pclk)
Figure 14–2
14–1. The clk125_in is used to capture the incoming receive data and also
rxdata
txdata
and is included in the file <variation name>.v or <variation
A
D
Q
Q
Mode 1
1
ENB
4
ENB
PLL
Q
Q
A
D
1
4
clk125_early tlp_clk_62p5
A
D
ENB
Q
Q
1
4
refclk
clk125_in
tlp_clk
MegaCore Function
PCI Express
December 2010 Altera Corporation
clk125_out
Chapter 14: External PHYs
External PHY Support