IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 283

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 15: Testbench and Design Example
BFM Procedures and Functions
Table 15–69.
Table 15–70.
Table 15–71.
December 2010 Altera Corporation
Arguments
Location
Syntax
Arguments
Location
Syntax
Arguments
find_mem_bar Procedure
dma_set_rclast Procedure
altpcietb_bfm_driver_chaining.v
Dma_set_rclast(bar_table, setup_bar, dt_direction, dt_rclast)
bar_table
setup_bar
dt_direction
dt_rclast
ebfm_display_verb Procedure
altpcietb_bfm_driver_chaining.v
ebfm_display_verb(msg_type, message)
msg_type
message
bar_table
allowed_bars
min_log2_size
sel_bar
dma_set_rclast Procedure
The dma_set_rclast procedure starts the DMA operation by writing to the endpoint
DMA register the value of the last descriptor to process (RCLast).
ebfm_display_verb Procedure
The ebfm_display_verb procedure calls the procedure ebfm_display when the global
variable DISPLAY_ALL is set to 1.
Address of the endpoint bar_table structure in BFM shared memory
BAR number to use
When 0 read, When 1 write
Last descriptor number
Message type for the message. Should be one of the constants
defined in
In VHDL, this argument is VHDL type string and contains the message text to
be displayed. In Verilog HDL, the message string is limited to a maximum of 100
characters. Also, because Verilog HDL does not allow variable length strings, this
routine strips off leading characters of 8'h00 before displaying the message.
Address of the endpoint bar_table structure in BFM shared memory
One hot 6 bits BAR selection
Number of bit required for the specified address space
BAR number to use
Table 15–39 on page
15–44.
PCI Express Compiler User Guide
15–55