IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 312

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

B–6
Table B–4. RX Data Phase Signals (Part 2 of 2)
PCI Express Compiler User Guide
rx_data<n>[63:0]
rx_be<n>[7:0]
rx_ws<n>
Note to
(1) For all signals, <n> is the virtual channel number which can be 0 or 1.
(1)
Table
Signal
B–4:
Transaction Examples Using Receive Signals
This section provides the following additional examples that illustrate how
transaction signals interact:
■
■
■
■
■
■
Transaction without Data Payload
Retried Transaction and Masked Non-Posted Transactions
Transaction Aborted
Transaction with Data Payload
Transaction with Data Payload and Wait States
Dependencies Between Receive Signals
I/O
O
O
I
Receive data bus. This bus transfers data from the link to the application layer. It is 2
DWORDS wide and is naturally aligned with the address in one of two ways, depending
on bit 2 of rx_desc.
■
■
■
■
This natural alignment allows you to connect rx_data[63:0] directly to a 64-bit datapath
aligned on a QW address (in the little endian convention).
Bit 2 is set to 1 (5 DWORD transaction)
Figure B–3.
Bit 2 is set to 0 (5 DWORD transaction)
Figure B–4.
Receive byte enable. These signals qualify data on rx_data[63:0]. Each bit of the
signal indicates whether the corresponding byte of data on rx_data[63:0] is valid.
These signals are not available in the ×8 IP core.
Receive wait states. With this signal, the application layer can insert wait states to
throttle data transfer.
rx_desc[2] (64-bit address) when 0: The first DWORD is located on rx_data[31:0].
rx_desc[34] (32-bit address) when 0: The first DWORD is located on bits
rx_data[31:0].
rx_desc[2] (64-bit address) when 1: The first DWORD is located on bits
rx_data[63:32].
rx_desc[34] (32-bit address) when 1: The first DWORD is located on bits
rx_data[63:32].
rx_data[63:32]
rx_data[63:32]
rx_data[31:0]
rx_data[31:0]
clk
clk
1
1
2
2
Description
3
3
DW 1
DW 0
DW 0
4
4
DW 3
DW 2
DW 1
DW 2
December 2010 Altera Corporation
5
5
DW 4
DW 3
DW 4
6
6
Descriptor/Data Interface
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