IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 197

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 11: Flow Control
Throughput of Posted Writes
Table 11–1. FC Update Loop Delay in Nanoseconds Components For Stratix II GX (Part 1 of 2)
December 2010 Altera Corporation
From decrement transmit credit consumed counter
to PCI Express Link.
From PCI Express Link until packet is available at
Application Layer interface.
From Application Layer draining packet to
generation and transmission of Flow Control (FC)
Update DLLP on PCI Express Link (assuming no
arbitration delay).
Delay Path
6. After an FC Update DLLP is created, it arbitrates for access to the PCI Express link.
7. The FC Update DLLP is received back at the original write requester and the
To allow the write requester to transmit packets continuously, the credit allocated
and the credit limit counters must be initialized with sufficient credits to allow
multiple TLPs to be transmitted while waiting for the FC Update DLLP that
corresponds to the freeing of credits from the very first TLP transmitted.
Table 11–1
Express IP core is implemented in a Stratix II GX device. The delay components are
independent of the packet length. The total delays in the loop increase with packet
length.
The FC Update DLLPs are typically scheduled with a low priority; consequently, a
continuous stream of application layer TLPs or other DLLPs (such as ACKs) can
delay the FC Update DLLP for a long time. To prevent starving the attached
transmitter, FC Update DLLPs are raised to a high priority under the following
three circumstances:
a. When the last sent credit allocated counter minus the amount of received
b. When an internal timer expires from the time the last FC Update DLLP was
c. When the credit allocated counter minus the last sent credit allocated
After arbitrating, the FC Update DLLP that won the arbitration to be the next item
is transmitted. In the worst case, the FC Update DLLP may need to wait for a
maximum sized TLP that is currently being transmitted to complete before it can
be sent.
credit limit value is updated. If packets are stalled waiting for credits, they can
now be transmitted.
data is less than MAX_PAYLOAD and the current credit allocated counter is
greater than the last sent credit counter. Essentially, this means the data sink
knows the data source has less than a full MAX_PAYLOAD worth of credits,
and therefore is starving.
sent, which is configured to 30 µs to meet the
resending FC Update DLLPs.
counter is greater than or equal to 25% of the total credits available in the RX
buffer, then the FC Update DLLP request is raised to high priority.
shows the delay components for the FC Update Loop when the PCI
Min
124
60
60
×8 Function
Max
168
68
68
Min
104
200
120
×4 Function
PCI Express Base Specification
Max
120
248
136
PCI Express Compiler User Guide
(Note
1),
Min
272
488
216
×1 Function
(Note 2)
for
Max
288
536
232
11–3