IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 75

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: IP Core Architecture
PCI Express Avalon-MM Bridge
Figure 4–10. PCI Express Avalon-MM Bridge
December 2010 Altera Corporation
Avalon Clock Domain
Control Register
Access Slave
■
The PCI Express Avalon-MM bridge supports the following TLPs:
■
Avalon-MM
Avalon-MM
Avalon-MM
Avalon-MM
Translator
Response
Translator
Rx Master
Response
Tx Slave
Rx Read
Control Register Access (CRA) Slave Module—This optional, 32-bit Avalon-MM
dynamic addressing slave port provides access to internal control and status
registers from upstream PCI Express devices and external Avalon-MM masters.
Implementations that use MSI or dynamic address translation require this port.
Tx Read
Memory write requests
Address
Address
Control & Status
Reg (CSR)
PCI Express Avalon-MM Bridge
PCI Express MegaCore Function
Crossing
Crossing
Domain
Domain
Clock
Clock
Clock Domain
Boundary
Sync
CRA Slave Module
Rx Master Module
Rx Master Module
PCI Express Clock Domain
Legacy Interrupt
Tx Slave Module
Rx Controller
Tx Controller
PCI Express
PCI Express
Generator
MSI or
PCI Express Compiler User Guide
PCI Link
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