IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 41

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
Compile for the Design
Compile for the Design
Reusing the Example Design
December 2010 Altera Corporation
Specify QSF Constraints
Pin Assignments for the Stratix IV (EP4SGX230KF40C2) Development Board (continued)
# Note reclk_free uses 100 MHz input
# On the S4GX Dev kit make sure that
#
#
set_instance_assignment -name IO_STANDARD LVDS -to free_100MHz
set_location_assignment PIN_AV22 -to free_100MHz
This section describes two additional constraints to improve performance in specific
cases.
■
■
To test your PCI Express IP core in hardware, your initial Quartus II compilation
includes all of the directories shown in
customized design, you can exclude the testbench directory from the Quartus II
compilation.
Complete the following steps to compile:
1. Ensure your preferred timing analyzer is selected. (Assignments Menu > Settings
2. On the Processing menu, click Start Compilation to compile your design.
To use this example design as the basis of your own design, replace the endpoint
application layer example shown in
design. Then, modify the BFM driver to generate the transactions needed to test your
application layer.
Constraints for Stratix IV GX ES silicon–add the following constraint to your .qsf
file:
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to
*wire_central_clk_div*_coreclkout
Constraints for design running at frequencies higher than 250 MHz:
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
> Timing Analysis).
This constraint aligns the PIPE clocks (core_clk_out) from each quad to reduce
clock skew in ×8 variants.
This constraint improves performance for designs in which asynchronous signals
in very fast clock domains cannot be distributed across the FPGA fast enough due
to long global network delays. This optimization performs automatic pipelining of
these signals, while attempting to minimize the total number of registers inserted.
SW4.5 = ON
SW4.6 = ON
Figure 2–5
Figure
2–4. After you have fully tested your
with your own application layer
PCI Express Compiler User Guide
2–15