IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 189

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 9: Optional Features
Instantiating Multiple PCI Express IP Cores
December 2010 Altera Corporation
Source Multiple Tcl Scripts
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1
To successfully combine multiple high-speed transceiver channels in the same quad,
they must have the same dynamic reconfiguration setting. To use the dynamic
reconfiguration capability for one transceiver instantiation but not another, in
Arria II GX, Stratix II GX, and Stratix IV GX devices, you must set reconfig_clk to 0
and reconfig_togxb to 3’b010 (in Stratix II GX devices) or 4’b0010 (in Arria II GX or
Stratix IV GX devices) for all transceiver channels that do not use the dynamic
reconfiguration capability.
If both IP cores implement dynamic reconfiguration, for Stratix II GX devices, the
ALT2GXB_RECONFIG megafunction instances must be identical.
To support the dynamic reconfiguration block, turn on Analog controls on the
Reconfig tab in the ALTGX or ALT2GXB MegaWizard Plug-In Manager.
Arria GX devices do not support dynamic reconfiguration However, the
reconfig_clk and reconfig_togxb ports appear in variations targeted to Arria GX
devices, so you must set reconfig_clk to 0 and reconfig_togxb to 3’b010.
If you use Altera-provided Tcl scripts to specify constraints for IP cores, you must run
the Tcl script associated with each generated PCI Express IP core. For example, if a
system has pcie1 and pcie2 IP core variations, and uses the pci_express_compiler.tcl
constraints file, then you must source the constraints for both IP cores sequentially
from the Tcl console after generation.
After you compile the design once, you can run the your pcie_constraints.tcl
command with the -no_compile option to suppress analysis and synthesis, and
decrease turnaround time during development.
In the MegaWizard Plug-In Manager flow, the script contains virtual pins for most
I/O ports on the PCI Express IP core to ensure that the I/O pin count for a device is
not exceeded. These virtual pin assignments must reflect the names used to connect to
each PCI Express instantiation.
PCI Express Compiler User Guide
9–7