IP-AGX-PCIE/4 Altera, IP-AGX-PCIE/4 Datasheet - Page 114

• Manufacturer Part Number: IP-AGX-PCIE/4
• Description: IP CORE - PCI Express X1 And X4 Lanes For Arria GX
• Manufacturer: Altera

Specifications of IP-AGX-PCIE/4

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–30
Table 5–10. Configuration MSI Control Status Register
Table 5–11. Configuration MSI Control Status Register Field Descriptions
PCI Express Compiler User Guide
15
[15:9]
[8]
[7]
[6:4]
[3:1]
[0]
reserved
Bit(s)
9
capability
reserved
mask
capability
64-bit
address
capability
multiples
message
enable
multiple
message
capable
MSI Enable
mask
8
Table 5–10
Table 5–11
Status Register.
Field
capability
outlines the use of the various fields of the Configuration MSI Control
shows the layout of the Configuration MSI Control Status Register.
address
64-bit
Per vector masking capable. This bit is hardwired to 0 because the function does not
support the optional MSI per vector masking using the Mask_Bits and
Pending_Bits registers defined in the
vector masking can be implemented using application layer registers.
64-bit address capable
■
■
Multiple message enable: This field indicates permitted values for MSI signals. For
example, if “100” is written to this field 16 MSI signals are allocated
■
■
■
■
■
■
■
■
Multiple message capable: This field is read by system software to determine the
number of requested MSI messages.
■
■
■
■
■
■
■
If set to 0, this component is not permitted to use MSI.
7
1: function capable of sending a 64-bit message address
0: function not capable of sending a 64-bit message address
000: 1 MSI allocated
001: 2 MSI allocated
010: 4 MSI allocated
011: 8 MSI allocated
100: 16 MSI allocated
101: 32 MSI allocated
110: Reserved
111: Reserved
000: 1 MSI requested
001: 2 MSI requested
010: 4 MSI requested
011: 8 MSI requested
100: 16 MSI requested
101: 32 MSI requested
110: Reserved
Field and Bit Map
6
multiple message enable
Description
PCI Local Bus Specification, Rev.
4
—
3
multiple message
capable
December 2010 Altera Corporation
Chapter 5: IP Core Interfaces
Avalon-ST Interface
1
MSI
enable
3.0. Per
0