XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 460

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Although Figure 118 depicts connections between the Transmit UTOPIA Interface block pins and the ATM Layer
2.3.5.1.2.9
In Figure 117, a simple illustration of the “Conceptual Multi-PHY” system consisting of two single-channel UNI
devices was presented. In reality, a given Multi-PHY system can or will consist of numerous “multi-channel”
UNI devices.
XRT94L33 can be thought of as consisting of four ATM UNIs within a single package (one for each STS-3c
port within the device).
It is important to note that although the XRT94L33 consists of a single “Receive UTOPIA Interface” block, the
XRT94L33 can be assigned four unique (4) Transmit UTOPIA Addresses as presented in Section _.
2.3.5.1.2.10
After the ATM Layer processor has “polled” each of the UNI devices, within its system, it must now select a
UNI, and begin reading ATM cell data from that device. The ATM Layer processor makes its selection and
begins the reading process by:
1. Applying the UTOPIA Address of the “target” UNI on the “UTOPIA Address Bus”.
2. Negate the RxUEnB* signal. This step causes the “addressed” UNI to recognize that it has been selected
to transmit the next set of ATM cell data to the ATM Layer processor.
3. Assert the RxUEnB* signal.
4. Check and insure that the RxUSoC output pin (of the selected UNI) pulses “high” when the first byte or
word of ATM cell data has been placed on the Receive UTOPIA Data Bus.
5. Begin reading the ATM Cell data in a byte-wide (or word-wide) manner from the Receive UTOPIA Data
bus.
Figure 119 presents a flow-chart that depicts the “UNI Device Selection and Read” process in Multi-PHY
operation.
Figure 119 Flow-Chart of the “UNI Device Selection and Read Procedure” for the Multi-PHY Operation
processor; the Transmit UTOPIA Interface operation, in the Multi-PHY mode, will not be discussed in this section.
Please see Section _ for a discussion on the Transmit UTOPIA Interface block during Multi-PHY operation.
The XRT94L33 is an example of this, being a “4-channel” UNI device.
ATM Layer Processor “polling” with the XRT94L33
Reading ATM Cell Data from a Different UNI
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
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Therefore, the