XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 402

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Receive ATM Cell Processor Block – Receive ATM Control Register – Byte 2 (Address = 0xN701)
Figure 96 Functional Block Diagram of the Receive ATM Cell Processor block
Each of these sub-blocks will be discussed in some detail below.
2.3.4.1
The HEC Byte Verification Block is the very first block (within the signal path of the Receive ATM Cell
Processor block) to receive and process ATM cell data. Figure 97 presents an illustration of the “Functional
Block Diagram” of the Receive ATM Cell Processor Block with the “HEC Byte Verification” block highlighted.
B
R/O
Receive UTOPIA
IT
Interface Block
0
7
Main Data Path
RxFIFO
RxFIFO
T
HE
HEC B
B
R/O
IT
0
6
YTE
Calculation
Calculation
V
Parity
Block
ERIFICATION
Parity
Block
B
R/O
IT
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
Unused
B
De-Scrambler
LOCK
Cell Payload
De-Scrambler
User Cell
Cell Payload
User Cell
Idle Cell
Filter
Block
B
Idle Cell
R/O
Filter
Block
Filter
Block
Block
Filter
IT
0
4
402
B
R/O
Cell Extraction
IT
Cell Insertion
Cell Extraction
0
Cell Insertion
Processor
Processor
Verification
3
Processor
Processor
HEC Byte
Verification
Buffer/
Buffer/
HEC Byte
Buffer/
Buffer/
Block
Block
Receive GFC
Nibble-Field
Receive GFC
Output I/F
Nibble-Field
Output I/F
B
R/O
IT
0
2
Microprocessor
Microprocessor
STS-3c/STS-12c
Processor Block
From Receive
Interface
Interface
Block
Block
POH
Processor
ATM Cell
Receive
Enable
B
R/W
IT
1
1
xr
Test Cell
Receiver
Enable
Mode
B
R/W
IT
0
0