XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 367

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Receive STS-3 Transport – Receive SD Set Monitor Interval – Byte 0 (Address = 0x113F)
STEP 2 – Setting the “SD Defect Declare B2 Error Threshold” to 1x10-9
Within 167 seconds, there will be [167 seconds • 622.08Mbits/second] = 103.9Gb of data that will have been
transmitted via an STS-12 data-stream.
As a consequence, if the BER is 1x10-9, then there will be [167 seconds • 622.08Mbits/second • 1x10-9
errors/bits] = 103.9 erred bits within a 167 second period.
As a consequence, we need to write the value 104 (or 0x0068) into the “Receive STS-3 Transport – Receive
SD Set Threshold” Registers as depicted below.
Receive STS-3 Transport – Receive SD SET Threshold – Byte 1 (Address = 0x1142)
Receive STS-3 Transport – Receive SD SET Threshold – Byte 0 (Address = 0x1143)
Based upon the configuration settings that were implemented within STEPS 1 and 2, the SD Detector will
declare the SD Defect condition anytime it detects 104 B2 byte errors within a given 167 second “SD Defect
Declare Monitor time” period.
Now, let’s suppose that this incoming STS-12 signal is “error-free”, and that the SD Detector is currently not
declaring the SD defect condition; and that it has currently talled 0 B2 byte errors during the current “SD
Defect Declaring Monitor time” period.
Now, let’s further suppose that a burst of errors (lasting 1us) occurs within this STS-12 data-stream. We will
also presume that the “timing” of this “error-burst” event is such that it straddles two STS-12 frames. If the
Receive STS-12 TOH Processor block is configured to accumulate B2 byte errors in a “per-bit” manner
(please see Section _ for a definition of “per-bit manner”) then the SD Detector can accumulate and tally as
much as 96 B2 byte errors/STS-12 x 2 STS-12 frames =) 192 B2 byte errors. In this example, this single
burst of errors within the incoming STS-12 signal will cause the SD Detector to declare the SD Defect (since it
has accumulated 192 B2 byte errors within a given 167 second “SD Defect Declare Monitor Time” period).
Occurrence whenever the Receive STS-3 TOH Processor block declares the SD Defect Condition
Anytime the Receive STS-3 TOH Processor block declares the SD Defect Condition, then it will do the
following.
•
B
B
B
R/W
R/W
R/W
It will generate the “Change of SD Defect Condition” Interrupt
IT
IT
IT
0
0
0
7
7
7
B
B
B
R/W
R/W
R/W
IT
IT
IT
1
0
1
6
6
6
B
B
B
R/W
R/W
R/W
IT
IT
IT
0
0
1
5
5
5
SD_SET_MONITOR_WINDOW[7:0]
SD_SET_THRESHOLD[15:8]
SD_SET_THRESHOLD[7:0]
B
B
B
R/W
R/W
R/W
IT
IT
IT
1
0
0
4
4
4
367
B
B
B
R/W
R/W
R/W
IT
IT
IT
1
0
1
3
3
3
B
B
B
R/W
R/W
R/W
IT
IT
IT
0
0
0
2
2
2
B
B
B
R/W
R/W
R/W
IT
IT
IT
0
0
0
1
1
1
XRT94L33
Rev.1.2.0.
B
B
B
R/W
R/W
R/W
IT
IT
IT
0
0
0
0
0
0