XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 177

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Transmit ATM Cell Processor – Interrupt Enable Register (Address = 0xNF0F)
Once the user has enabled the “Detection of Parity Error” Interrupt, then the Transmit ATM Cell Processor
block will generate an interrupt anytime it detects a Parity Error within a given byte (or 16-bit word) in a given
incoming “User Cell”. Whenever the Transmit ATM Cell Processor block generates this interrupt, it will
indicate so by doing all of the following.
Transmit ATM Cell Processor – Interrupt Status Register (Address = 0xNF0B)
2.2.5.6
For Performance Monitoring purposes, the user can keep track of the number of parity errors that have been
detected over time, by periodically polling and reading out the contents of the “Transmit ATM Cell Processor –
Parity Error Count” Register. This register is a 32-bit wide, RESET-upon-READ register, that is incremented
each time the Transmit ATM Cell Processor block detects a parity error in an incoming User Cell. This
register will increment up until it reaches the value of “0xFFFFFFFF”; at this point it will saturate at this value
(e.g., cease to increment), until read again.
B
B
R/O
R/O
IT
1. By toggling the “INT*” output pin “LOW.
2. By setting Bit 0 (Detection of Parity Error Interrupt Status), within the “Transmit ATM Cell Processor –
IT
0
0
7
7
Unused
Unused
Interrupt Status Register” to “1”, as depicted below.
C
OUNTING
B
B
R/O
R/O
IT
IT
0
0
6
6
P
ARITY
Extraction
Extraction
Interrupt
Interrupt
Enable
Status
B
B
RUR
R/W
Cell
Cell
IT
IT
0
0
E
5
5
RRORS
Insertion
Insertion
Interrupt
Interrupt
Enable
Status
B
B
RUR
R/W
Cell
Cell
IT
IT
0
0
4
4
177
Extraction
Extraction
Overflow
Overflow
Interrupt
Interrupt
Memory
Memory
Enable
Status
B
B
RUR
R/W
Cell
Cell
IT
IT
0
0
3
3
Cell Insertion
Cell Insertion
Overflow
Overflow
Interrupt
Interrupt
Memory
Memory
Enable
Status
B
B
RUR
R/W
IT
IT
0
0
2
2
Detection of
Detection of
HEC Byte
HEC Byte
Interrupt
Interrupt
Enable
Status
B
Error
B
Error
RUR
R/W
IT
IT
0
0
1
1
XRT94L33
Detection of
Detection of
Parity Error
Parity Error
Interrupt
Interrupt
Enable
Status
Rev.1.2.0.
B
B
RUR
R/W
IT
IT
1
1
0
0