XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 152

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
2.2.1.1
The ATM Layer processor will interface to the Transmit UTOPIA Interface block via the following pins.
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Each of these signals is briefly discussed below.
TxUData[15:0] - Transmit UTOPIA Data Bus inputs
The ATM Layer Processor will write its ATM Cell Data into the Transmit UTOPIA Interface block, by placing it,
in a byte-wide (or 16-bit word-wide) manner on these input pins. The Transmit UTOPIA Data Bus can be
configured to operate in the “8-bit wide” or “16-bit wide” mode (See Section _). If the “8-bit wide” mode is
selected, then only the TxUData[7:0] input pins are active and capable of accepting ATM cell data from the
ATM Layer Processor. If the “16-bit wide” mode is selected, the all 16 input pins (e.g., TxUData[15:0]) are
active. The Transmit UTOPIA Data bus is tri-stated while the active-low TxUEnB* (Transmit UTOPIA Data
Bus - Write Enable) input signal is “high”. Therefore, the ATM Layer processor must assert this signal (e.g.,
toggling TxUEnB* “low”) in order write the cell data, on the Transmit UTOPIA Data bus, into the Transmit
UTOPIA Interface Block. The data on the Transmit UTOPIA Data Bus is sampled and latched into the
Transmit UTOPIA Interface block, on the rising edge of the Transmit UTOPIA Interface Block Clock signal,
TxUClk.
Additionally, the Transmit UTOPIA Interface block will only process one cell worth of data (e.g., 52, 53 or 54
bytes, as configured via the Cell_Size_Sel[1:0] option - See Section _), following the latest assertion of the
TxUSoC (Transmit-Start of Cell) pin. Afterwards, the Transmit UTOPIA Data bus will become tri-stated and
will cease to process any more data from the ATM Layer Processor until the next assertion of the TxUSoC
pin. Once the Transmit UTOPIA Interface block reaches this condition, it will ignore the assertions of the
TxUEnB* pin, and will keep the Transmit UTOPIA Data bus input pins tri-stated until the ATM Layer
Processor pulses the TxUSoC input pin, once again.
If the Transmit UTOPIA Interface block detects a “runt” cell (e.g., if the amount of data that is read into the
TxUFIFO is less than that configured via the “Cell_Size_Sel[1:0]” option), then the Transmit UTOPIA Interface
block will discard this cell, and resume normal operation.
TxUAddr[4:0] - Transmit UTOPIA Address Bus inputs
These input pins are only used when the XRT94L33 is operating in the Multi-PHY mode. Therefore, for more
information on the Transmit UTOPIA Address Bus, please see Section _.
TxUClk - Transmit UTOPIA Interface Block - Clock signal input pin
The Transmit UTOPIA Interface block uses this signal to sample and latch the data on the Transmit UTOPIA
Data bus into the Transmit UTOPIA Address block (for Multi-PHY operation) into the Transmit UTOPIA
Interface block. This clock signal can run at frequencies of up to 50 MHz.
TxUData[15:0] -
TxUAddr[4:0] -
TxUClk
TxUClkO
TxUSoC
TxUPrty
TxUEnB*
TxUClav/TFullB*
THE PINS OF THE TRANSMIT UTOPIA BUS INTERFACE
Transmit UTOPIA Address Bus Input pins
TxFIFO Cell Available
Transmit UTOPIA Interface block clock input pin
Transmit UTOPIA Data Bus - Write Enable input pin
Transmit UTOPIA - Odd Parity Input pin
Transmit UTOPIA Data Bus Input pins
Transmit UTOPIA Interface block clock output pin
Transmit “Start of Cell” indicator input pin
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
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