XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 349

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
According to Telecordia GR-253-CORE, a Line Terminating Equipment must declare the AIS-L (Line AIS)
defect condition whenever it determines that bits 6, 7 and 8 (within the K2 byte) of the incoming STS-3 data-
stream, are each set to “1” for five consecutive STS-3 frames.
Figure 84 presents an illustration of the “AIS-L Defect Declaration/Clearance” State Machine diagram that is
used by the Receive STS-3 TOH Processor blocks within the XRT94L33.
Figure 84 Illustration of the “AIS-L Defect Declaration/Clearance” State Machine diagram
2.3.1.4.1
The Receive STS-3 TOH Processor block is capable of declaring and clearing the AIS-L defect condition. If
the Receive STS-3 TOH Processor block receives at least five consecutive STS-3 frames, in which bits 6, 7
and 8 (within the K2 byte) are each set to “1”, then it will declare the AIS-L defect condition. The Receive
STS-3c TOH Processor block will indicate that it is declaring the AIS-L defect condition, by doing all of the
following.
• It will set Bit 0 (AIS-L Defect Declared) within the Receive STS-3 Transport Status Register – Byte 1, to “1”
as illustrated below.
Receive STS-3 Transport Status Register – Byte 1 (Address = 0x1106)
B
IT
7
Receive STS-3/STS-12 TOH Processor block
Receives five (5) consecutive frames in which bits
6, 7, and 8 (within the K2 byte) are NOT set to the
Pattern [1, 1, 1]
How the Receive STS-3 TOH Processor Block Declares the AIS-L Defect Condition
B
IT
6
Defect is
Defect is
Cleared
AIS-L
Cleared
AIS-L
Unused
B
IT
5
B
IT
4
Receive STS-3/STS-12 TOH Processor
block receives five (5) consecutive frames
In which bits 6, 7 and 8 (within the K2 byte)
are set to the pattern [1, 1, 1]
349
B
IT
3
Defect is
Declared
Defect is
Declared
AIS-L
Mismatch
Message
Declared
AIS-L
Section
Defect
Trace
B
IT
2
Message
Declared
Unstable
Section
Defect
Trace
B
IT
1
XRT94L33
Declared
Defect
AIS_L
Rev.1.2.0.
B
IT
0