XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 340

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
It will clear Bit 1 (SEF Defect Declared) within the “Receive STS-3 Transport Status Register – Byte 0” to “0”,
as depicted below.
Receive STS-3 Transport Status Register – Byte 0 (Address = 0x1107)
5. It will generate the “Change in SEF Defect Condition” interrupt. The XRT94L33 will indicate that it is
Receive STS-3 Transport Interrupt Status Register – Byte 0 (Address = 0x110B)
2.3.1.3.2
Once the Receive STS-3 TOH Processor block reaches this state, then it has already cleared the “SEF
Defect Condition”. For the duration that the Receive STS-3 TOH Processor block is operating in the “SEF =
0, LOF = 1” state, the Receive STS-3 TOH Processor block will be testing the Framing Alignment bytes (A1
and A2) within the incoming STS-3 signal, in order to determine if it can clear the “LOF” defect condition.
In this case, the Receive STS-3 TOH Processor will test the Framing Alignment bytes (within the incoming
STS-3 data-stream) a “User-Selectable” number of SONET frame periods.
Processor does not detect any Framing Byte errors (during this “user-selected test” period), then it will clear
the LOF defect.
The user can specify the number of consecutive STS-3 frame periods, that the Receive STS-3 TOH
Processor block must remain in the “SEF = 0, LOF = 1” state, by writing the appropriate value into Bits 3
through 0 (In-Sync Threshold[3:0]) within the Receive STS-3 Transport – In Sync Threshold Register; as
depicted below.
Receive STS-3 Transport – In Sync Threshold Register (Address = 0x112B)
Declared
Change of
SF Defect
Condition
Interrupt
Defect
RDI-L
B
Status
R/O
B
RUR
B
generating this interrupt by doing the following.
Toggling the “INT*” input pin “low” and
Setting Bit 1 (Change of SEF Defect Condition Interrupt Status), within the “Receive STS-3 Transport
R/O
IT
0
IT
IT
0
0
7
7
7
Interrupt Status Register – Byte 0” as depicted below.
Declared
Unstable
The SEF = 0, LOF = 1 State
S1 Byte
Defect
Change of
SD Defect
B
Condition
R/O
Interrupt
IT
0
Status
B
RUR
B
R/O
6
IT
IT
0
0
6
6
Unused
Unstable
Declared
K1, K2
Defect
B
Byte
R/O
Detection of
REI-L Error
IT
0
Interrupt
Status
5
B
RUR
B
R/O
IT
IT
0
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
Declared
Defect
B
R/O
SF
IT
0
Detection of
4
Interrupt
B2 Byte
Status
B
Error
B
RUR
R/O
IT
IT
0
0
4
4
SD Defect
Declared
B
340
R/O
IT
0
3
Detection of
Interrupt
B1 Byte
Status
B
Error
RUR
B
R/W
IT
IT
X
0
3
3
Declared
Defect
B
LOF
R/O
IT
1
2
LOF Defect
Change of
Condition
Interrupt
In-Sync Threshold[3:0]
Status
B
B
RUR
R/W
IT
IT
X
0
Declared
Defect
2
2
B
SEF
R/O
IT
0
1
If the Receive STS-3 TOH
SEF Defect
Change of
Condition
Interrupt
Status
B
RUR
B
R/W
Declared
IT
IT
X
1
Defect
B
LOS
R/O
1
1
xr
IT
0
0
LOS Defect
Change of
Condition
Interrupt
Status
B
RUR
B
R/W
IT
IT
X
0
0
0