XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 401

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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XRT94L33
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Rev.1.2.0.
A Very Brief Description of the Receive ATM Cell Processor Block
The Receive ATM Cell Processor block receives an un-delineated stream of ATM cell data from the Receive
STS-3c POH Processor block. As this data-stream passes through the Receive ATM Cell Processor block it
will initially pass through the “HEC Byte Verification” Block which is responsible for Cell Delineation and HEC
Byte Verification.
The Receive ATM Cell Processor receives a continuous unframed stream of ATM cells from the Receive
STS-3c POH Processor block. As the Receive ATM Cell Processor block receives this ATM cell data, it will
then perform all of the following functions on this ATM cell data.
• Cell Delineation
• HEC Byte Verification
• Cell Payload De-Scrambling (optional)
• Idle Cell Filtering
• User Cell Filtering
Finally, all ATM cells that successfully make it through the “above-mentioned” processing will be written into
the “RxFIFO” within the Receive UTOPIA Interface block, where it can be read out via the Receive UTOPIA
Data Bus (by the ATM Layer Processor block).
Functional Description of the Receive ATM Cell Processor
This section presents an in-depth functional description of the Receive ATM Cell Processor block.
Additionally, this section presents all of the configuration options associated with the Receive ATM Cell
Processor block.
The Receive ATM Cell Processor block consists of the following functional blocks.
• HEC Byte Verification block
• Cell Payload De-Scrambler block
• Idle Cell Filter block
• Receive User Cell Filter block
• Receive Cell Extraction Buffer/Processor
• Receive Cell Insertion Buffer/Processor
• Parity Calculation and Insertion block
• Receive GFC Nibble-Field Serial Output Port
Figure 96 presents an illustration of the functional block diagram of the Receive ATM Cell Processor block
with each of these “above-mentioned” functional blocks noted.
Each of these “sub-blocks” will be discussed in some detail below. However, before we get too much into the
detailed functional description of the Receive ATM Cell Processor block; the user MUST note that the
Receive ATM Cell Processor block will NOT even function unless the user enables the “Receive ATM Cell
Processor” block for operation. The user can enable the Receive ATM Cell Processor block by setting Bit 1
(Receive ATM Cell Processor Enable), within the “Receive ATM Cell Processor Block – Receive ATM Control
Register – Byte 2” to “1” as depicted below.
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