XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 202

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
The “HEC Byte Calculation & Insertion” block receives either filtered User Cells or Idle cells from the
upstream circuitry, within the Transmit ATM Cell Processor block. As it receives these cells, the “HEC Byte
Calculation & Insertion” block can be configured to perform any of the following actions on these cells.
•
•
•
•
Computing and Verifying HEC Bytes of incoming cells
As the HEC Byte Calculation & Insertion block receives ATM cells, it takes the first four bytes of each cell and
computes a CRC-8 value via the generating polynomial x
Note:
Configuring the HEC Byte Calculation & Insertion block to Check for HEC Byte Errors
If the user wishes to configure the Transmit ATM Cell Processor block to compute, verify and flag HEC byte
errors in cells originating from upstream circuitry, then they must write a “1” into Bit 6 (HEC Byte Check
Enable) within the “Transmit ATM Control – Byte 0, as depicted below.
Transmit ATM Control – Byte 0 (Address = 0xNF03)
If the user implements this configuration option, then the HEC Byte Calculation & Insertion Block will compute
and verify the HEC byte, within all ATM cells that it receives from the Idle Cell Generator and the Transmit
User Cell Filter blocks. If the HEC Byte Calculation & Insertion Block detects a HEC byte error, then the
Transmit ATM Cell Processor block will generate the “Detection of HEC Byte Error” Interrupt. The Transmit
ATM Cell Processor block will indicate that it is generating this interrupt by doing all of the following.
•
•
Transmit ATM Cell Processor – Interrupt Status Register (Address = 0xNF0B)
HEC Byte
B
R/O
Invert
B
R/W
To compute and verify the HEC bytes of incoming cells from upstream circuitry within the Transmit ATM
Cell Processor block
To regenerate the HEC byte (e.g., to compute and insert the HEC bytes of incoming cells)
To add the Coset Polynomial to the HEC byte, prior to transmission via the “Transmit Data Path”
A detailed description of the HEC Byte Calculation & Insertion block is presented below.
It will toggle the “INT*” output pin “LOW”.
The Transmit ATM Cell Processor block will set Bit 1 (Detection of HEC Byte Error Interrupt Status),
within the “Transmit ATM Cell Processor – Interrupt Status Register” as depicted below.
IT
IT
0
7
7
Unused
The user has the option to have the coset polynomial x
insert this newly modified CRC-8 value into the fifth octet position within the cell before transmission. This
option will be discussed later in this section.
B
R/O
HEC Byte
IT
Enable
Check
B
R/W
6
IT
1
6
Extraction
Interrupt
Status
Parity Check
B
RUR
Cell
IT
Enable
B
5
R/W
IT
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
Insertion
Interrupt
Discard Cell
Status
upon Parity
B
RUR
Cell
IT
B
Error
R/W
4
IT
X
4
202
Extraction
Overflow
Interrupt
Memory
8
Odd Parity
Status
B
RUR
Cell
+ x
6
IT
B
R/W
+ x
3
IT
X
2
3
+ x + 1.
4
+ x
2
Cell Insertion
+ 1 modulo-2 added to the CRC-8 byte and,
Overflow
Interrupt
Memory
Status
B
RUR
B
IT
R/O
IT
0
2
2
Unused
Detection of
HEC Byte
Interrupt
Status
B
Error
RUR
B
R/O
IT
IT
0
1
1
xr
Cell Payload
Detection of
Parity Error
Scramble
Interrupt
Enable
Status
B
RUR
B
R/W
IT
IT
X
0
0