XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 265

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Figure 47: A Simple Illustration of the “External Circuit” being interfaced to the “TxPOH Input Port”
Note:
• Whenever the “external circuit” samples both the “TxPOHEnable_n” and “TxPOHFrame_n” output pins
“high”, then it should enter a “WAIT STATE” (e.g., where it waits for 25 periods of “TxPOHClk_n” to elapse).
Afterwards, the external circuit should exit this “WAIT STATE” and then place the very first bit of the
“outbound” RDI-P bit-fields onto the “TxPOH_n” input pin, upon the very next falling edge of “TxPOHClk_n”.
This data bit will be sampled and latched into the “Transmit SONET POH Processor” block circuitry, upon the
very next rising edge of “TxPOHClk_n”.
Note:
• Afterwards, the “external circuit” should serially place the remaining two bits (of the RDI-P bits) onto the
“TxPOH_n” input pin, upon each of the next two falling edges of “TxPOHClk_n”.
• The “external circuit” should then revert back to continuously sampling the states of the “TxPOHEnable_n”
and “TxPOHFrame_n” output pins and repeat the above-mentioned process.
Figure 48 presents an illustration of the “TxPOH Input Interface” waveforms, when the “external circuit” is
writing the RDI-P bits into the “TxPOH Input Port”.
Figure 48 Illustration of the “TxPOH Input Interface” waveforms, when the “External Circuit” is writing
the “RDI-P bits” into the “TxPOH Input Port”.
The “TxPOHIns_n” line (in Figure 47) is “dashed” because controlling this signal is not necessary if the user has
This “WAIT STATE” period is necessary because the G1 byte is the 4th byte within the POH; and bit 7 (which is
executed “STEP 1” above.
the very first RDI-P bit to be latched into the External Input Interface is the second bit within the G1 byte to be
processed).
XRT95L34 Device
TxPOHEnable_n
TxPOHFrame_n
TxPOHClk_n
TxPOHIns_n
TxPOH_n
265
TxPOHData_OUT
TxPOHFrame_IN
TxPOHEnable_IN
TxPOH_INSERT
TxPOHClk_IN
External Circuit
XRT94L33
Rev.1.2.0.