XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 334

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
The Receive STS-3 TOH Processor block can be configured to receive the incoming STS-3 data via the
Receive STS-3 PECL Interface block or via the Receive STS-3 Telecom Bus Interface block. A detailed
discussion on the Receive STS-3 PECL Interface block can be found in Section 8.0. Likewise, a detailed
discussion on the Receive STS-3 Telecom Bus Interface can be found in Section 7.0.
2.3.1.1
The Receive STS-3 TOH Processor block permits the user to optionally descramble the incoming STS-3
data-stream.
2.3.1.2
According to Telecordia GR-253-CORE, a SONET Network Element must monitor all incoming SONET
signals (before de-scrambling) for an “All Zeros” pattern.
condition whenever it continues to receives an “All Zeros” pattern for 100µs or longer. Further, the Network
Element must not declare an LOS condition, if it receives the “All Zeros” pattern for 2.3µs or less.
2.3.1.2.1
The Receive STS-3c TOH Processor block is capable of declaring and clearing the LOS condition. Further,
the Receive STS-3c TOH Processor block register set permits the user to define the LOS declaration criteria,
by writing the appropriate data into the “Receive STS-3c Transport – LOS Threshold Value – MSB” and “LSB”
registers, as illustrated below.
Receive STS-3c Transport – LOS Threshold Value - MSB (Address = 0x112E)
Receive STS-3c Transport – LOS Threshold Value - LSB (Address = 0x112F)
The contents of these two registers, combined, reflects the number of consecutive “All Zeros” bytes (prior to
de-scrambling) that the Receive STS-3 TOH Processor block must detect before it declares the LOS defect
condition.
For STS-3c applications, if the user wishes to comply with the LOS Declaration Requirements, per Telecordia
GR-253-CORE, then they must write a value that ranges between 0x000F and 0x0288 into the “Receive STS-
3 Transport – LOS Threshold Value – MSB/LSB” Register.
If the Receive STS-3c TOH Processor block detects the appropriate number of consecutive “All Zeros”, then it
will declare the LOS defect condition. The Receive STS-3c TOH Processor block will indicate that it is
declaring the LOS defect condition, by doing all of the following.
• It will set Bit 0 (LOS Defect Declared) within the Receive STS-3 Transport Status Register – Byte 0, to “1”
as illustrated below.
B
B
R/W
R/W
IT
IT
1
1
7
7
DESCRAMBLING OF DATA
LOS DECLARATION AND CLEARANCE CRITERIA SONET R
LOS D
How the Receive STS-3c TOH Processor Block Declares the LOS Defect
B
B
R/W
R/W
EFECT
IT
IT
1
1
6
6
B
B
R/W
R/W
IT
IT
1
1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
LOS_THRESHOLD[15:8]
LOS_THRESHOLD[7:0]
B
B
R/W
R/W
IT
IT
1
1
4
4
334
B
B
R/W
R/W
IT
IT
1
1
The Network Element must declare an LOS
3
3
B
B
R/W
R/W
IT
IT
1
1
EQUIREMENTS FOR
2
2
B
B
R/W
R/W
IT
IT
1
1
1
1
xr
D
ECLARING THE
B
B
R/W
R/W
IT
IT
1
1
0
0