XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 159

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Note:
3. Apply the Odd-Parity value of this first byte (or word), currently residing on the Transmit UTOPIA
This should be done concurrently with pulsing the TxUSoC input pin “high”.
Note:
4. Assert the “Transmit UTOPIA Data Bus” - Write Enable Signal, TxUEnb*.
This step should also be done concurrently with pulsing the TxUSoC input pin “high”.
When writing the subsequent bytes (word) of the cell, the ATM Layer Processor must repeatedly exercise
Steps 3 and 4, of the above list.
Since the XRT94L33 is always operating in the Cell-Level Handshake mode, then the ATM Layer Processor
should check the level of the TxUClav signal, as it nears completion of writing in a given cell. If “TxUClav” is
“high” then the ATM Layer Processor can finish writing the current cell into the “Transmit UTOPIA Interface”
block. Afterwards, the ATM Layer Processor may proceed to write in the contents of the very next “outbound”
ATM cell into the Transmit UTOPIA Interface block.
Conversely, if “TxUClav” is “low” then the ATM Layer Processor should finish writing the current ATM cell data
into the “Transmit UTOPIA Interface” block.
“TxUEnb*” input pin and halt writing any more ATM cell data into the “Transmit UTOPIA Interface” block, until
the TxUClav output pin toggles “high” again.
The above-mentioned procedure is also depicted in Flow-Chart Form in Figure 13 and in Timing Diagram
form in Figure 14.
Data Bus, to the TxUPrty input pin.
The Transmit UTOPIA Interface block will sample and latch the state of the TxUSoC input pin upon the rising
The Transmit UTOPIA Interface block will sample and latch the state of the “TxUPrty” input pin upon the rising
edge of TxUClk. Therefore, if the TxUClk to TxUSoC output delay (of the ATM Layer Processor) is 1ns or more,
then the ATM Layer Processor should update the state of the “TxUSoC” input pin (of the XRT94L33) upon the
rising edge of TxUClk.
edge of TxUClk. Therefore, if the TxUClk to TxUPrty output delay (of the ATM Layer Processor) is 1ns or more,
then the ATM Layer Processor should update the state of the “TxUPrty” input pin (of the XRT94L33) upon the
rising edge of “TxUClk”.
Afterwards, the ATM Layer Processor must negate the
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XRT94L33
Rev.1.2.0.