XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 341

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
The value that the user writes into these bit-fields reflects the number of STS-3 frame periods that the
Receive STS-3 TOH Processor block must reside within the “SEF = 0, LOF = 1” state and test the Framing
Alignment bytes, within the incoming STS-3 data-stream.
If the Receive STS-3 TOH Processor block does not detect the “User Selectable” number of consecutive “un-
erred” STS-3 frames, then it will remain in the “SEF = 0, LOF = 1” state and will continue to test for the “user-
selectable” number of consecutive un-erred STS-3 frame. If the Receive STS-3 TOH Processor block were to
detect Framing Byte errors in four consecutive STS-3 frames, then it will declare the “SEF” defect and will
transition back into the “SEF = 1, LOF = 1” state.
If the Receive STS-3 TOH Processor block receives this “User-Selectable” number of consecutive “unerred”
STS-3 frames, then it will clear the “LOF defect” and will transition into the “In-Frame” state.
As the Receive STS-3 TOH Processor block transitions from the “SEF = 0, LOF = 1” state to the “In-Frame”
state, it will do all of the following.
It will clear Bit 2 (LOF Defect Declared) within the “Receive STS-3 Transport Status Register – Byte 0” to “0”
Receive STS-3 Transport Status Register – Byte 0 (Address = 0x1107)
It will generate the “Change in LOF Defect Condition” interrupt.
Receive STS-3 Transport Interrupt Status Register – Byte 0 (Address = 0x110B)
Change of
SF Defect
Condition
Declared
Interrupt
Defect
Status
RDI-L
B
B
RUR
as depicted below.
R/O
generating this interrupt by doing the following.
IT
IT
0
0
7
7
a. Toggling the “INT*” input pin “LOW”.
b. Setting Bit 2 (Change of LOF Defect Condition Interrupt Status), within the “Receive STS-3
Change of
SD Defect
Condition
Unstable
Declared
Interrupt
S1 Byte
Transport Interrupt Status Register – Byte 0” as depicted below.
Defect
Status
B
B
RUR
R/O
IT
IT
0
0
6
6
Detection of
K1, K2 Byte
REI-L Error
Declared
Unstable
Interrupt
Defect
Status
B
B
RUR
R/O
IT
IT
0
0
5
5
Detection of
SF Defect
Declared
Interrupt
B2 Byte
Status
B
B
Error
RUR
R/O
IT
IT
0
0
4
4
341
Detection of
SD Defect
Declared
Interrupt
B1 Byte
Status
Error
B
B
RUR
R/O
IT
IT
0
0
3
3
The XRT94L33 will indicate that it is
LOF Defect
Change of
Condition
Declared
Interrupt
Defect
Status
B
B
RUR
LOF
R/O
IT
IT
0
0
2
2
SEF Defect
Change of
Condition
Declared
Interrupt
Defect
Status
B
B
RUR
SEF
R/O
IT
IT
0
1
1
1
XRT94L33
LOS Defect
Change of
Condition
Declared
Interrupt
Defect
Status
Rev.1.2.0.
B
B
RUR
LOS
R/O
IT
IT
0
0
0
0