XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 365

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Receive STS-3 Transport – Receive SD Set Monitor Interval – Byte 1 (Address = 0x113E)
Receive STS-3 Transport – Receive SD Set Monitor Interval – Byte 0 (Address = 0x113F)
Once the user has executed these two steps, then the “SD Declaration Criteria” will be as summarized below.
•
•
Hence, the Receive STS-3 TOH Processor block will accumulate B2 byte errors over a 16ms period.
At this point, the Receive STS-3 TOH Processor block will proceed to count B2 byte errors. Based upon the
“above-mentioned” configuration selections, if the Receive STS-3 TOH Processor block detects 15 or more
B2 byte errors, within a given 16ms period then it will declare the SD defect condition. Conversely, if the SD
Detector detects less than 15 B2 byte errors within this 16ms period, then it will NOT declare the SD Defect
condition.
Error Burst Filtering of B2 Byte Errors for Declaration of the SD Defect Condition
In some applications it may be necessary to insure that the SD defect condition is declared based upon the
long-term performance characteristics of a given incoming STS-3 signal, and is NOT induced by a single
“burst of errors” occurring within this STS-3 signal. An example of where this feature might be useful is
whenever one implements APS (Automatic Protection Switching) in response to the declaration of the SD
Defect Condition.
“otherwise” error-free STS-3 signal) to result in APS switching to a redundant STS-3 signal, and thereby
temporarily (and needlessly) disrupting ATM or PPP traffic across this APS event.
As a consequence, the SD Detector within the Receive STS-3 TOH Processor block contains an “error-burst”
filter which is set by selecting the appropriate “SD Defect B2 Byte Error Burst” limit.
Setting the “SD Defect B2 Byte Error Burst” Limit
As mentioned above, the user can specify the “SD Defect Declare Monitor” Time Interval (e.g., the amount of
time that the SD Detector will accumulate B2 byte errors, when determining whether to declare the SD defect
or not). This particular “SD Defect Declare Monitor Time” interval is sub-divided into eight (8) “sub-interval”
periods. The “Error Burst filter” permits the user to specify an upper limit to the number of B2 byte errors that
the SD detector can accumulate during a given “sub-interval” period; when determining whether or not to
declare the SD defect condition. The user can set the “Error Burst” filter by writing the appropriate value into
the “Receive STS-3 Transport – Receive SD Burst Error Tolerance – Byte 1 & Byte 0” registers as depicted
below.
B
B
R/W
R/W
The “SD Defect Declare B2 Byte Error” Threshold = 0x0F (or 15) B2 Errors.
The SD Defect Declare Monitor Time Period = 0x10 (or 16ms)
IT
IT
0
0
7
7
B
B
R/W
R/W
IT
IT
0
0
In this situation, it is undesirable to permit a single error-burst (which occurs in an
6
6
B
B
R/W
R/W
IT
IT
0
0
5
5
SD_SET_MONITOR_WINDOW[15:8]
SD_SET_MONITOR_WINDOW[7:0]
B
B
R/W
R/W
IT
IT
0
1
4
4
365
B
B
R/W
R/W
IT
IT
0
0
3
3
B
B
R/W
R/W
IT
IT
0
0
2
2
B
B
R/W
R/W
IT
IT
0
0
1
1
XRT94L33
Rev.1.2.0.
B
B
R/W
R/W
IT
IT
0
0
0
0