XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 161

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Figure 14 Timing Diagram of ATM Layer Processor writing ATM Cell data into the Transmit UTOPIA
Data Bus, (Single - PHY Mode)
Notes regarding Figure 14:
1. The Transmit UTOPIA Data Bus is configured to be 16 bits wide. Hence, the data, which the ATM Layer
processor places on the Transmit UTOPIA Data Bus, is expressed in terms of 16-bit words: W0 - W26.
2. The Transmit UTOPIA Interface Block is configured to handle 54 bytes/cell. Hence, Figure 24 illustrates
the ATM Layer processor writing 27 words (W0 through W26) for each ATM cell.
Final Comments on Single-PHY Operation
The important thing to note about the Single-PHY mode is that the TxUClav pin is used as a data flow control
pin, and has a role somewhat similar to RTS (Request To Send) in RS-232 based data transmission. The
TxUClav pin will have a slightly different role when the XRT94L33 is operating in the Multi-PHY mode.
The ATM Layer processor is expected to poll the TxUClav output pin during the last four “TxUClk” periods
(while writing a given ATM cell into the Transmit UTOPIA Interface block) prior to writing the next ATM cell to
the TxFIFO.
2.2.1.3.6
The XRT94L33 permits the user to configure it to operate in the “Multi-PHY” Mode.
accomplished by setting Bit 6 (Multi-PHY Mode), within the “Transmit UTOPIA Control Register – Byte 0” to
“1” as depicted below.
Transmit UTOPIA Control Register – Byte 0, Address = 0x0483
Note:
In the “Multi-PHY” operating mode, the ATM Layer processor may be writing data into and reading data from
several UNI (e.g., PHY-Layer) devices in parallel. Figure 12 presents an illustration of a simple “Multi-PHY
System” consisting of a single ATM Layer Processor being interfaced to two (2) UNI devices. When the
TxUData [15:0]
UTOPIA
Level
B
R/W
IT
1
TxUClav
TxUEnB *
TxUSoC
TxUClk
7
This configuration setting does not apply to the Receive UTOPIA Interface block. Therefore, the user will also
need to configure the Receive UTOPIA Interface block into the “Multi-PHY” Mode, as described in Section _.
Multi PHY Operation
W26
Multi-PHY
1
Mode
B
R/W
IT
1
W0
6
2
W1
Back Polling
3
Back-to-
Enable
B
R/W
IT
0
W2
5
4
Access
Status
Direct
B
R/W
IT
0
W22
4
24
161
W23
25
B
Data Bus Width[1:0]
R/W
Transmit UTOPIA
IT
1
W24
3
26
W25
27
B
R/W
IT
1
W26
2
28
X
29
B
R/W
Cell_Size_Sel[1:0]
IT
X
X
1
30
This can be
XRT94L33
Rev.1.2.0.
B
R/W
IT
X
0