XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 244

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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XRT94L33
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Rev.1.2.0.
Figure 40) is “dashed” because controlling this signal is not necessary if the user has executed “STEP 1” above.
• Whenever the “external circuit” samples both the “TxPOHEnable_n” and “TxPOHFrame_n” output pins
“high”, then it should enter a “WAIT STATE” (e.g., where it will wait for 40 periods of “TxPOHClk_n” to
elapse). Afterwards, the external circuit should exit this “WAIT STATE” and then place the very first bit (e.g.,
the most significant bit) of the “outbound” H4 byte onto the “TxPOH_n” input pin, upon the very next falling
edge of “TxPOHClk_n”. This data bit will be sampled and latched into the “Transmit STS-3c POH Processor”
block circuitry, upon the very next rising edge of “TxPOHClk_n”.
Note:
This “WAIT STATE” period is necessary because the H4 byte is the sixth byte within the POH.
• Afterwards, the “external circuit” should serially place the remaining seven bits (of the H4 byte) onto the
“TxPOH_n” input pin, upon each of the next seven falling edges of “TxPOHClk_n”.
• The “external circuit” should then revert back to continuously sampling the states of the “TxPOHEnable_n”
and “TxPOHFrame_n” output pins and repeat the above-mentioned process.
Figure 41 presents an illustration of the “TxPOH Input Interface” waveforms, when the “external circuit” is
writing the H4 byte into the “TxPOH Input Port”.
Figure 41 Illustration of the “TxPOH Input Interface” waveforms, when the “External Circuit” is writing
the “H4 byte” into the “TxPOH Input Port”.
2.2.7.3.8
SUPPORT/HANDLING OF THE Z3 BYTE
The Transmit STS-3c POH Processor block permits the user to control the value of the H4 byte by either of
the following options.
• Setting and controlling the “outbound” Z3 Byte via Software
• Setting and controlling the “outbound” Z3 Byte via the “TxPOH Input Port”
The details and instructions for using either or these features are presented below.
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