XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 361

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Receive STS-3 Transport Control Register – Byte 0 (Address = 0x1103)
The detection of B2 byte errors also plays a role in some of the other following functions.
•
•
Each of these items will be discussed in some detail in the next few sections.
2.3.1.12.3
2.3.1.12.4
2.3.1.13
The Receive STS-3 TOH Processor block is capable of declaring and clearing the SD defect condition.
Further, the Receive STS-3 TOH Processor block register set permits the user to define both the “SD Defect
Declaration” and “Clearance” criteria.
Each Receive STS-3 TOH Processor block contains an SD Detector. The SD Detector accumulates B2 byte
errors over a “user-defined” monitoring period of time. If the number of B2 errors (accumulated over this
“user-defined” period of time) exceeds a user-defined “SD Declaration B2 Byte Error threshold”, then the SD
Detector will declare the “SD” Defect Condition.
Similarly, if the SD Defect is currently being declared, then the “SD Detector” will continue to accumulate B2
byte errors over another “user-defined” monitor period of time. If the number of B2 byte errors (accumulated
over this “user-defined” period of time) is less than a “user-defined SD Defect Clearance B2 Byte Error”
threshold, then the SD Detector will clear the SD Defect condition.
It should be noted that the Receive STS-3 TOH Processor block (within the XRT94L33) permits the user to
independently specify the “SD Defect Declaration B2 Byte Error” Threshold and the “SD Defect Clearance B2
Byte Error” Threshold. As a consequence, the user can implement some sort of hysteresis within the SD
defect declaration or clearance thresholds. In order to further enhance the user’s ability to specify the SD
defect declaration and clearance thresholds, the user can also independently specify monitoring times that
are to be used in order to declare or clear the SD defect condition.
2.3.1.13.1
Prior to describing the behavior of the SD Detector, it is imperative to review the types of B2 byte errors that
can be accumulated for the sake of SD defect declaration or clearance. The Receive STS-3 TOH Processor
block can be configured to tally B2 byte errors in one of two-different manners.
• On a “per-bit” basis
• On a “per-frame” basis
If the user configures the Receive STS-3 TOH Processor block to “tally” B2 byte errors on a “per-bit” basis,
then it will declare an error for each bit (within the incoming B2 byte) that is determined to be in error. In this
case, the Receive STS-3 TOH Processor block can declare as many as 24 B2 byte errors, per STS-3 frame
(e.g., when all 8 bit, within each of the 3 incoming B2 bytes, are in error).
Unused
B
R/O
The Transmission of the REI-L (Line – Remote Error Indicator) in the “upstream” direction back out the to
the Remote Terminal Equipment.
The Declaration and Clearance of the SD (Signal Degrade) and SF (Signal Fail) defect conditions.
IT
0
7
THE SD (SIGNAL DEGRADE) DECLARATION AND CLEARANCE CRITERIA
Transmission of REI-L in response to Detection of B2 Byte Errors
B2 Byte Performance Monitoring
The Types of B2 Byte Errors
SF Detect
Enable
B
R/W
IT
0
6
SD Detect
Enable
B
R/W
IT
0
5
Descramble
Disable
B
R/W
IT
0
4
361
SDH/SONET*
B
R/W
IT
0
3
REI-L Error
B
Type
R/W
IT
0
2
B2 Error
B
Type
R/W
IT
0
1
XRT94L33
B1 Error
Rev.1.2.0.
B
Type
R/W
IT
0
0