XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 153

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
TxUClkO – Transmit UTOPIA Interface Block Clock Output signal
If the “Transmit UTOPIA Clock De-Skewing” PLL is enabled, then the ATM Layer Processor can use this
signal to clock out the contents of the “outbound” ATM cells, and to assert the UTOPIA Address (during Multi-
PHY operation). Similar to the “TxUClk” signal, this signal can run at frequencies up to 50MHz.
TxUEnB* - Transmit UTOPIA Data Bus - Write Enable input
The Transmit UTOPIA Data Bus is tri-stated while this input signal is negated. Therefore, the ATM Layer
Processor must assert this “active-low” signal (toggle it “low”) in order to write the byte (or word) on the
Transmit UTOPIA Data Bus, into the Transmit UTOPIA Interface block.
TxUPrty - Transmit UTOPIA - Odd Parity Bit input pin
The ATM Layer Processor is expected to compute the odd-parity value of each byte (or word) of ATM Cell
data that it intends to place on the Transmit UTOPIA Data bus. The ATM Layer Processor is then expected
to apply this parity value at the TxUPrty pin, while the corresponding byte (or word) is present on the Transmit
UTOPIA Data Bus. This signal, along with the corresponding byte (or word) of ATM cell data will be routed to
the Transmit ATM Cell Processor block for “Transmit UTOPIA parity verification”.
TxUSoC - Transmit UTOPIA - “Start of Cell” Indicator
The ATM Layer processor is expected to pulse this input signal “high”, for one clock period of TxUClk, when
the first byte (or word) of a given ATM cell is present on the Transmit UTOPIA Data Bus. This signal must be
kept “low” at all other times.
Note:
Example -1
For example, if the user configures the Transmit UTOPIA Interface block to process 53 bytes per cell; then
following the assertion of the TxUSoC pin (which is coincident with the placement of the first byte of the cell
on the Transmit UTOPIA Data bus), the Transmit UTOPIA Interface block will read in and process 52 more
bytes of data via the Transmit UTOPIA data bus resulting in a total of 53 bytes being processed. After the
Transmit UTOPIA Interface block has read in the 53rd byte, it will no longer read in any more data from the
ATM Layer Processor, (even if the “TxUEnb*” input pin is pulled “low”) until the TxUSoC pin has been
asserted.
TxUClav/TFullB* - Tx FIFO Cell Available/TxFIFO Full*
This output signal is used to provide some data flow control between the ATM Layer processor and the
Transmit UTOPIA Interface block. Please See Section _ for more information regarding this signal.
2.2.1.2
S
The XRT94L33 permits the user to configure the Transmit UTOPIA Interface block in either of the following
“UTOPIA Levels”.
• UTOPIA Level 3
• UTOPIA Level 1 or 2
The user can configure the Transmit UTOPIA Interface block within the XRT94L33 to operate in the
appropriate UTOPIA Level, by writing the appropriate value into Bit 7 (UTOPIA Level) within the “Transmit
UTOPIA Control Register”, as depicted below.
ELECTING THE
Once the ATM Layer Processor has pulsed the TxUSoC pin “high”, the Transmit UTOPIA Interface Block will
proceed to read in and process only one cell of data (e.g., 52, 53, or 54 bytes, as configured via the
“Cell_Size_Sel[1:0]” option - See Section _) via the Transmit UTOPIA Data Bus. Afterwards, the Transmit
UTOPIA Interface block will cease to process any more data from the ATM Layer Processor until the TxUSoC
pin has been pulsed “high” once again. This phenomenon is more clearly defined in “Example - 1” below.
C
ONFIGURATION
UTOPIA L
EVEL
O
PTIONS WITH THE
T
RANSMIT
153
UTOPIA I
NTERFACE BLOCK
XRT94L33
Rev.1.2.0.