XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 264

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
into bits 5 through 7 (of the G1 byte) within the “outbound” STS-1 SPE. The bit-format of the “Transmit
SONET Path – G1 Byte Value” register (with the appropriate bits “shaded”) is presented below.
Transmit SONET Path – Transmit G1 Byte Value Register (Address = 0xN99F)
In this mode, the user can transmit an “un-erred” indicator by setting Bits 3 through 1 (within the Transmit
SONET Path – Transmit G1 Byte Value” register) to [0, 0, 0]. Conversely, the user can now transmit an
“erred” indicator by setting Bits 3 through 1 (within the “Transmit SONET Path – Transmit G1 Byte Value”
register) to some value other than [0, 0, 0].
Configuring the Transmit SONET POH Processor block to transmit the RDI-P Indicator, via the
“TxPOH_n” input port.
The user can configure the Transmit SONET POH Processor block to transmit the RDI-P (per external input
port) by executing the following steps.
STEP 1 – Write the value “[1, 0]” into Bits 3 and 4 (RDI-P Insertion Type[1:0]) within the “Transmit
SONET Path – SONET Control Register – Byte 0”, as depicted below.
Transmit SONET Path – SONET Control Register – Byte 0 (Address = 0xN983)
This step configures the “Transmit SONET POH Processor” block to set the value of the RDI-P bit-fields
(within the outbound STS-1 SPE) based upon the data that it receives via the “TxPOH_n” input port. In this
mode, the Transmit SONET POH Processor block will accept the value, corresponding to the RDI-P bit-fields
(via the “TxPOH_n Input Port”) and it will write this data into the “outbound” STS-1 SPE data-stream.
STEP 2 – Begin providing the values of the “outbound” RDI-P bit-fields to the “TxPOH_n”
The procedure for applying the RDI-P bit-values to the “TxPOH_n” input port is presented below.
Using the “TxPOH” Input Port to insert the RDI-P bit values into the outbound STS-1 SPE data-stream
If the user intends to externally insert the RDI-P bits into the outbound STS-1 SPE, via the “TxPOH_n” input
port, then they must design some external circuitry (which can be realized in an ASIC, FPGA or CPLD
solution) to do to the following.
• Continuously sample the “TxPOHEnable_n” and the “TxPOHFrame_n” output pins upon the rising edge of
the “TxPOHClk_n” output clock signal.
A simple illustration of this “external circuit” being interfaced to the “TxPOH Input Port” is presented below in
Figure 47.
F2 Insertion
B
B
Type
R/W
R/W
IT
IT
0
0
7
7
REI-P Insertion Type[1:0]
B
B
R/W
R/W
IT
IT
0
0
6
6
B
B
R/W
R/W
IT
IT
0
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
Transmit_G1_Byte_Value[7:0]
RDI-P Insertion Type[1:0]
B
B
R/W
R/W
IT
IT
0
1
4
4
264
B
B
R/W
R/W
IT
X
IT
0
3
3
Insertion
C2 Byte
B
B
Type
R/W
R/W
IT
IT
X
0
2
2
Unused
B
B
R/W
R/O
IT
X
IT
0
1
1
xr
input port.
Transmit
Enable
AIS-P
B
B
R/W
R/W
IT
IT
0
0
0
0