XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 442

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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XRT94L33
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Rev.1.2.0.
• Compute and present the odd-parity value of the byte (or word) that is present at the Receive UTOPIA Data
Bus.
• Indicate the boundaries of cells, to the ATM Layer processor, by pulsing the RxUSoC (Receive Start of
Cell) pin each time the first byte (or word) of a new cell is present on the Receive UTOPIA Data Bus.
The Receive UTOPIA Interface Block consists of the following sub-blocks:
• Receive UTOPIA Output Interface
• Receive UTOPIA Cell FIFO (Rx FIFO)
• Receive UTOPIA FIFO Manager
The Receive UTOPIA Interface block consists of an output interface complying to the “UTOPIA Level 2
Interface Specifications”, and the RxFIFO. The width of the Receive UTOPIA Data Bus is user-configurable
to be either 8 or 16 bits. The Receive UTOPIA Interface block also allows the ATM Layer processor to
perform parity checking on all data that it receives from it (the Receive UTOPIA Interface block), over the
Receive UTOPIA Data bus. The Receive UTOPIA Interface block computes the odd-parity of each byte (or
word) that it will place on the Receive UTOPIA data bus. The Receive UTOPIA Interface block will then
output the value of this computed parity at the RxPrty pin, while the corresponding data byte (word) is present
at the RxData[15:0] output pins.
The Receive UTOPIA Interface block can be configured to process 52, 53, and 54 bytes per cell; and will
assert the RxUSoC (Receive “Start of Cell”) output pin at the cell boundaries. If the Receive UTOPIA
Interface block detects a “runt” cell (e.g., a cell that is smaller than what the Receive UTOPIA Interface block
has been configured to handle), it will generate an interrupt to the local µP, discard this “runt” cell, and
resume normal operation.
The physical size of the Rx FIFO is sixteen cells. The incoming data (from the Receive Cell Processor) is
written into the Rx FIFO, where it can be read in and processed by the ATM Layer Processor. A FIFO
Manager maintains the Rx FIFO and indicates the FIFO Empty and FIFO Full to the local µP. Additionally the
FIFO Manager will indicate that ATM Cell Data is available in the RxFIFO, by asserting the RxUClav output
pin.
The following sections discusses each functional sub-block of the Receive UTOPIA Interface block in detail.
Additionally, these sections discuss many the of the features associated with the Receive UTOPIA Interface
block as well as how the user can optimize these features in order to suit his/her application needs. Detailed
discussion of Single-PHY and Multi-PHY operation will be presented in its own section even though it involves
the use of all of these functional blocks.
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