XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 319

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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XRT94L33
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
Rev.1.2.0.
•
Whenever the “external circuit” samples the “TxPOHFrame_n” output pin “high” and also the
“TxPOHEnable_n” pin “low”, then it should enter a “WAIT STATE” (e.g., where it waits for __ periods of
“TxPOHClk_n” to elapse). Afterwards, the external circuit should exit this “WAIT STATE” and then place the
very first bit (e.g., the most significant bit) of the “outbound” E1 byte onto the “TxPOH_n” input pin, upon the
very next falling edge of “TxPOHClk_n”. This data bit will be sampled and latched into the “Transmit STS-3c
POH Processor” block circuitry, upon the very next rising edge of “TxPOHClk_n”.
Note:
This “WAIT STATE” period is necessary because the E1 byte is the _ byte within the TOH.
• Afterwards, the “external circuit” should serially place the remaining seven bits (of the E1 byte) onto the
“TxPOH_n” input pin, upon each of the next seven falling edges of “TxPOHClk_n”.
• The “external circuit” should then revert back to continuously sampling the states of the “TxPOHEnable_n”
and “TxPOHFrame_n” output pins and repeat the above-mentioned process.
Figure 69 presents an illustration of the “TxPOH Input Interface” waveforms, when the “external circuit” is
writing the E1 byte into the “TxPOH Input Port”.
Figure 69 Illustration of the “TxPOH Input Interface” waveforms, when the “External Circuit” is writing
the “E1 byte” into the “TxPOH Input Port”
2.2.9.5.7
SUPPORT/HANDLING OF THE F1 BYTE
The Transmit STS-3c TOH Processor block permits the user to control the value of the F1 byte, which is to be
transmitted via the “outbound” STS-3c data-stream by either or the following options.
• Setting and controlling the F1 byte via software
• Setting and controlling the F1 byte via the “TxPOH Input Port”
The details and instructions for using either of these features are presented below.
2.2.9.5.7.1
Setting and Controlling the outbound F1 byte via Software
The Transmit STS-3c TOH Processor block permits the user to specify the contents of the E1 byte within the
outbound STS-3c data-stream via software command.
The user can configure the Transmit STS-3c TOH Processor block to accomplish this by performing the
following steps.
STEP 1 – Write the value “1” into Bit 3 (F1 Insert Method) within the “Transmit STS-3c Transport –
SONET Transmit Control Register – Byte 1, as depicted below.
Transmit STS-3cTransport – SONET Transmit Control Register – Byte 1 (Address = 0x1902)
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
IT
IT
IT
IT
IT
IT
IT
IT
Reserved
E2 Insert
E1 Insert
F1 Insert
S1 Insert
K1K2 Insert
M0M1 Insert
Method
Method
Method
Method
Method
Method[1]
R/O
R/O
R/W
R/W
R/W
R/W
R/W
R/W
0
0
X
0
1
X
X
X
The step configures the Transmit STS-3c TOH Processor block to read out the contents of the “Transmit
STS-3c Transport – F1 Byte Value Register, and load this value into the F1 byte position within each
outbound STS-3c data-stream.
STEP 2 – Write the desired byte values (for the outbound F1 byte) into the “Transmit STS-3c
Transport – F1 Byte Value Register.
The bit-format for this register is presented below.
Transmit STS-3c Transport – Transmit F1 Byte Value Register (Address = 0x1943)
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