XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 30

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
D11
E10
B8
A5
A6
A7
TxPOHClk_0
TxPOHClk_1
TxPOHClk_2
TxPOH_0
TxPOH_1
TxPOH_2
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
O
I
CMOS
TTL
Transmit Path Overhead Input Port – Input pin.
These input pins permit the user to insert the POH data into
each of the 3 Transmit SONET POH Processor blocks (for
insertion and transmission via the “outbound” STS-3 signal.
If the user is only inserting POH data via these input pins:
In this mode, the external circuitry (which is being interfaced to
the “Transmit Path Overhead Input Port” is suppose to monitor
the following output pins;
• TxPOHFrame_n
• TxPOHEnable_n
• TxPOHClk_n
The “TxPOHFrame_n” output pin will toggle “high” upon the
rising
“TxPOHClk_n” period prior to the “TxPOH” port being ready to
accept and process the first bit within J1 byte (e.g., the first
POH byte).
“high” for eight consecutive “TxPOHClk_n” periods.
external circuitry should use this pin to note STS-1 SPE frame
boundaries.
The “TxPOHEnable_n” output pin will toggle “high” upon the
rising
“TxPOHClk_n” period prior to the “TxPOH” port being ready to
accept and process the first bit within a given POH byte.
To externally insert a given POH byte:
Transmit Path Overhead Input Port – Clock Output pin:
These output pins, along with “TxPOH_n”, “TxPOHEnable_n”,
“TxPOHIns_n” and “TxPOHFrame” function as the “Transmit
Path Overhead (TxPOH) Input Port”.
The “TxPOHFrame” and “TxPOHEnable” output pins are
updated upon the falling edge this clock output signal. The
“TxPOHIns_n” input pins and the data residing on the
“TxPOH_n” input pins are sampled upon the next falling edge
of this clock signal.
(1) assert the “TxPOHIns_n” input pin by toggling it “high”,
(2) place the value of the first bit (within this particular POH
This data bit will be sampled upon the very next falling edge
of “TxPOHClk_n”. The external circuitry should continue to
keep the “TxPOHIns_n” input pin “high” and advancing the
next bits (within the POH bytes) upon each rising edge of
“TxPOHClk_n”.
30
and
byte) on this input pin upon the very next rising edge of
“TxPOHClk_n”.
edge
edge
The “TxPOHFrame_n” output pin will remain
of
of
“TxPOHClk_n”
“TxPOHClk_n”
approximately
approximately
xr
one
The
one