XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 370

• Manufacturer Part Number: XRT94L33IB-L
• Description: IC MAPPER DS3/E3/STS-1 504TBGA
• Manufacturer: Exar Corporation

Specifications of XRT94L33IB-L

• Applications: Network Switches
• Interface: Bus
• Voltage - Supply: 3.14 V ~ 3.47 V
• Package / Case: 504-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT94L33
Rev.1.2.0.
Example of Defining the SD Defect Clearance Criteria
Suppose that the user writes in the value “0x0008” into the “Receive STS-3 Transport – Receive SD Defect
Clear Threshold” Registers; as depicted below.
Receive STS-3 Transport – Receive SD CLEAR Threshold – Byte 1 (Address = 0x1146)
Receive STS-3 Transport – Receive SD CLEAR Threshold – Byte 0 (Address = 0x1147)
Additionally, now suppose that the user writes in the value “0x000100” into the “Receive STS-3 Transport –
Receive SD Clear Monitor Interval” Registers; as depicted below.
Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 2 (Address = 0x1159)
Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 1 (Address = 0x115A)
Receive STS-3 Transport – Receive SD Clear Monitor Interval – Byte 0 (Address = 0x115B)
Once the user has executed these two steps, then the “SD Defect Clearance Criteria” will now be as
summarized below.
•
•
Hence, in order to determine whether to clear the SD defect condition or not, the SD Detector (within the
Receive STS-3 TOH Processor block) will tally B2 byte errors over this 256ms period.
B
B
B
B
B
R/W
R/W
R/W
R/W
R/W
The SD Defect Clear B2 Byte Error Threshold = 0x08 (or 8) B2 Byte Errors
The SD Defect Clear Monitor period = 0x100 (or 256ms)
IT
IT
IT
IT
IT
0
0
0
0
0
7
7
7
7
7
B
B
B
B
B
R/W
R/W
R/W
R/W
R/W
IT
IT
IT
IT
IT
0
0
0
0
0
6
6
6
6
6
B
B
B
B
B
R/W
R/W
R/W
R/W
R/W
IT
IT
IT
IT
IT
0
0
0
0
0
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
5
5
5
5
5
SD_CLEAR_MONITOR_WINDOW[23:16]
SD_CLEAR_MONITOR_WINDOW[15:8]
SD_CLEAR_MONITOR_WINDOW[7:0]
SD_CLEAR_THRESHOLD[15:8]
SD_CLEAR_THRESHOLD[7:0]
B
B
B
B
B
R/W
R/W
R/W
R/W
R/W
IT
IT
IT
IT
IT
0
0
0
0
0
4
4
4
4
4
370
B
B
B
B
B
R/W
R/W
R/W
R/W
R/W
IT
IT
IT
IT
IT
0
1
0
0
0
3
3
3
3
3
B
B
B
B
B
R/W
R/W
R/W
R/W
R/W
IT
IT
IT
IT
IT
0
0
0
0
0
2
2
2
2
2
B
B
B
B
B
R/W
R/W
R/W
R/W
R/W
IT
IT
IT
IT
IT
0
0
0
0
0
1
1
1
1
1
xr
B
B
B
B
B
R/W
R/W
R/W
R/W
R/W
IT
IT
IT
IT
IT
0
0
0
1
0
0
0
0
0
0