XRT94L33IB-L Exar Corporation, XRT94L33IB-L Datasheet - Page 219
XRT94L33IB-L
Manufacturer Part Number
XRT94L33IB-L
Description
IC MAPPER DS3/E3/STS-1 504TBGA
Manufacturer
Exar Corporation
Specifications of XRT94L33IB-L
Applications
Network Switches
Interface
Bus
Voltage - Supply
3.14 V ~ 3.47 V
Package / Case
504-LBGA
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XRT94L33IB-L
Manufacturer:
Exar Corporation
Quantity:
10 000
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3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC DATA SHEET
STEP 1 – Write the value [0, 0] into Bits 3 and 4 (RDI-P Insertion Type[1, 0]) within the “Transmit STS-
3c Path – SONET Control Register – Byte 0” as depicted below.
Transmit STS-3c Path – SONET Control Register – Byte 0 (Address = 0x1983)
This step configures the “Transmit STS-3c POH Processor” block to automatically set bits 5 through 7 (of the
G1 byte) within the outbound STS-3c SPE; to the appropriate “RDI-P value” based upon receive conditions as
detected by the corresponding “Receive STS-3c POH Processor” block.
STEP 2 – Write the appropriate value into Bits 3 through 1 (PLM-P RDI-P CODE[2:0]) within the
“Transmit STS-3c Path – RDI-P Control Register – Byte 2” as illustrated below.
Transmit STS-3c Path – RDI-P Control Register – Byte 2 (Address = 0x19C9)
By writing this particular value into these three bit-fields, the user is specifying the value that the “Transmit
STS-3c POH Processor” block will set the RDI-P bit-fields (within the “outbound G1 byte) to, whenever the
corresponding Receive STS-3c POH Processor block declares the PLM-P condition.
STEP 3 – Set Bit 0 (Transmit RDI-P upon PLM-P) within the “Transmit STS-3c Path – RDI-P Control
Register – Byte 2” to “1”, as illustrated below.
Transmit STS-3c Path – RDI-P Control Register – Byte 2 (Address = 0x19C9)
This step configures the Transmit STS-3c POH Processor block to automatically transmit the RDI-P indicator
(per the values written into Bits 3 through 1; within this register), anytime the corresponding Receive STS-3c
POH Processor block detects the “PLM-P” condition.
F2 Insertion
B
Type
B
B
R/W
R/W
R/W
IT
IT
IT
0
0
0
7
7
7
LCD-P RDI-P Code[2:0]
LCD-P RDI-P Code[2:0]
REI-P Insertion Type[1:0]
B
B
B
R/W
R/W
R/W
IT
IT
IT
0
0
0
6
6
6
B
B
B
R/W
R/W
R/W
IT
IT
IT
0
0
0
5
5
5
RDI-P upon
RDI-P upon
RDI-P Insertion Type[1:0]
Transmit
Transmit
LCD-P
LCD-P
B
B
B
R/W
R/W
R/W
IT
IT
IT
0
0
0
4
4
4
219
B
B
B
R/W
R/W
R/W
IT
IT
IT
X
X
0
3
3
3
PLM-P RDI-P Code[2:0]
PLM-P RDI-P Code[2:0]
Insertion
C2 Byte
B
Type
B
B
R/W
R/W
R/W
IT
IT
IT
0
X
X
2
2
2
Unused
B
B
B
R/W
R/W
R/W
IT
IT
IT
X
X
0
1
1
1
XRT94L33
RDI-P upon
RDI-P upon
Transmit
Transmit
Transmit
Enable
PLM-P
PLM-P
AIS-P
Rev.1.2.0.
B
B
B
R/W
R/W
R/W
IT
IT
IT
0
0
1
0
0
0
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